Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328210 |
1 |
|
|
T1 |
4674 |
|
T2 |
18 |
|
T4 |
2 |
auto[1] |
376594 |
1 |
|
|
T4 |
778 |
|
T13 |
538 |
|
T14 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
176772 |
1 |
|
|
T1 |
1150 |
|
T2 |
8 |
|
T4 |
208 |
lower_val |
173920 |
1 |
|
|
T1 |
1203 |
|
T2 |
6 |
|
T4 |
215 |
zero_val |
1975 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
352534 |
1 |
|
|
T1 |
2332 |
|
T2 |
8 |
|
T4 |
370 |
lower_val |
352266 |
1 |
|
|
T1 |
2342 |
|
T2 |
10 |
|
T4 |
410 |
zero_val |
4 |
1 |
|
|
T134 |
2 |
|
T135 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40872 |
1 |
|
|
T1 |
583 |
|
T2 |
3 |
|
T4 |
1 |
higher_val |
higher_val |
auto[1] |
47562 |
1 |
|
|
T4 |
104 |
|
T13 |
76 |
|
T14 |
608 |
higher_val |
lower_val |
auto[0] |
40861 |
1 |
|
|
T1 |
567 |
|
T2 |
5 |
|
T12 |
80 |
higher_val |
lower_val |
auto[1] |
47475 |
1 |
|
|
T4 |
103 |
|
T13 |
75 |
|
T14 |
543 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T134 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T135 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40667 |
1 |
|
|
T1 |
589 |
|
T2 |
3 |
|
T12 |
59 |
lower_val |
higher_val |
auto[1] |
46600 |
1 |
|
|
T4 |
107 |
|
T13 |
66 |
|
T14 |
621 |
lower_val |
lower_val |
auto[0] |
40481 |
1 |
|
|
T1 |
614 |
|
T2 |
3 |
|
T12 |
51 |
lower_val |
lower_val |
auto[1] |
46172 |
1 |
|
|
T4 |
108 |
|
T13 |
69 |
|
T14 |
557 |
zero_val |
higher_val |
auto[0] |
712 |
1 |
|
|
T1 |
4 |
|
T4 |
1 |
|
T13 |
5 |
zero_val |
higher_val |
auto[1] |
294 |
1 |
|
|
T4 |
1 |
|
T13 |
2 |
|
T14 |
2 |
zero_val |
lower_val |
auto[0] |
686 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
283 |
1 |
|
|
T4 |
1 |
|
T13 |
3 |
|
T14 |
2 |