Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101159633	1			T1	567553		T2	303		T4	228697
all_pins[1]	101159633	1			T1	567553		T2	303		T4	228697
all_pins[2]	101159633	1			T1	567553		T2	303		T4	228697

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302572745	1			T1	169911		T2	898		T4	685497
values[0x1]	906154	1			T1	3545		T2	11		T4	594
transitions[0x0=>0x1]	903822	1			T1	3545		T2	11		T4	594
transitions[0x1=>0x0]	903842	1			T1	3545		T2	11		T4	594

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100644719	1			T1	564008		T2	292		T4	228103
all_pins[0]	values[0x1]	514914	1			T1	3545		T2	11		T4	594
all_pins[0]	transitions[0x0=>0x1]	514901	1			T1	3545		T2	11		T4	594
all_pins[0]	transitions[0x1=>0x0]	67	1			T120	3		T146	3		T103	3
all_pins[1]	values[0x0]	101159553	1			T1	567553		T2	303		T4	228697
all_pins[1]	values[0x1]	80	1			T120	3		T146	3		T103	3
all_pins[1]	transitions[0x0=>0x1]	71	1			T120	3		T146	3		T103	3
all_pins[1]	transitions[0x1=>0x0]	391151	1			T13	4334		T23	391		T24	671
all_pins[2]	values[0x0]	100768473	1			T1	567553		T2	303		T4	228697
all_pins[2]	values[0x1]	391160	1			T13	4334		T23	391		T24	671
all_pins[2]	transitions[0x0=>0x1]	388850	1			T13	4306		T23	391		T24	671
all_pins[2]	transitions[0x1=>0x0]	512624	1			T1	3545		T2	11		T4	594