Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T99 4 T100 7 T101 4
all_values[1] 287 1 T99 4 T100 7 T101 4
all_values[2] 287 1 T99 4 T100 7 T101 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 476 1 T99 5 T100 12 T101 9
auto[1] 385 1 T99 7 T100 9 T101 3


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 394 1 T99 4 T100 10 T101 4
auto[1] 467 1 T99 8 T100 11 T101 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 508 1 T99 5 T100 13 T101 7
auto[1] 353 1 T99 7 T100 8 T101 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 67 1 T100 2 T101 1 T139 2
all_values[0] auto[0] auto[0] auto[1] 29 1 T100 1 T101 1 T139 1
all_values[0] auto[0] auto[1] auto[0] 41 1 T140 1 T141 1 T142 2
all_values[0] auto[0] auto[1] auto[1] 30 1 T99 1 T100 1 T140 2
all_values[0] auto[1] auto[0] auto[1] 61 1 T101 2 T139 1 T143 4
all_values[0] auto[1] auto[1] auto[1] 59 1 T99 3 T100 3 T140 1
all_values[1] auto[0] auto[0] auto[0] 87 1 T99 1 T100 2 T101 1
all_values[1] auto[0] auto[1] auto[0] 81 1 T100 2 T101 1 T140 2
all_values[1] auto[1] auto[0] auto[1] 66 1 T99 1 T100 3 T101 1
all_values[1] auto[1] auto[1] auto[1] 53 1 T99 2 T101 1 T139 2
all_values[2] auto[0] auto[0] auto[0] 68 1 T99 3 T100 4 T101 1
all_values[2] auto[0] auto[0] auto[1] 33 1 T101 2 T143 2 T144 1
all_values[2] auto[0] auto[1] auto[0] 50 1 T143 1 T145 1 T141 2
all_values[2] auto[0] auto[1] auto[1] 22 1 T100 1 T140 2 T139 1
all_values[2] auto[1] auto[0] auto[1] 65 1 T140 1 T139 2 T143 1
all_values[2] auto[1] auto[1] auto[1] 49 1 T99 1 T100 2 T101 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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