Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.43	95.88	92.30	100.00	69.42	94.11	98.84	96.43

Total test records in report: 1253

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html

T1251	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1680411631			Jun 13 12:34:43 PM PDT 24	Jun 13 12:34:45 PM PDT 24	90907076 ps
T1252	/workspace/coverage/cover_reg_top/18.kmac_intr_test.2785864848			Jun 13 12:35:12 PM PDT 24	Jun 13 12:35:14 PM PDT 24	25971545 ps
T1253	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.187991990			Jun 13 12:35:04 PM PDT 24	Jun 13 12:35:07 PM PDT 24	80210590 ps

Test location	/workspace/coverage/default/38.kmac_stress_all.1636116206
Short name	T13
Test name
Test status
Simulation time	1001052137553 ps
CPU time	1738.23 seconds
Started	Jun 13 12:39:49 PM PDT 24
Finished	Jun 13 01:08:48 PM PDT 24
Peak memory	438908 kb
Host	smart-06a635e6-78ad-4088-b0d1-66c00878dbee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1636116206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.1636116206 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_stress_all/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.3643068460
Short name	T84
Test name
Test status
Simulation time	536512225 ps
CPU time	3.07 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:44 PM PDT 24
Peak memory	215160 kb
Host	smart-ac1bdc6a-104d-443c-8435-16293fec7652
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643068460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac _shadow_reg_errors_with_csr_rw.3643068460 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/default/1.kmac_sec_cm.2046633015
Short name	T5
Test name
Test status
Simulation time	3813787699 ps
CPU time	52.7 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:38:12 PM PDT 24
Peak memory	242024 kb
Host	smart-c6c53035-0928-4da0-8542-0bd6d47fe971
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046633015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2046633015 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/1.kmac_sec_cm/latest

Test location	/workspace/coverage/default/26.kmac_stress_all_with_rand_reset.1428829600
Short name	T32
Test name
Test status
Simulation time	506442185917 ps
CPU time	2807.15 seconds
Started	Jun 13 12:38:20 PM PDT 24
Finished	Jun 13 01:25:08 PM PDT 24
Peak memory	421096 kb
Host	smart-2f7fd01a-00ff-45b5-b4ca-eabe2f3b598b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1428829600 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all_with_rand_reset.1428829600 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/18.kmac_key_error.81536568
Short name	T22
Test name
Test status
Simulation time	5453042900 ps
CPU time	5.44 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:38:08 PM PDT 24
Peak memory	215572 kb
Host	smart-8234064b-ea07-43d9-ac89-d75b42624991
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81536568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.81536568 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_error.72618619
Short name	T24
Test name
Test status
Simulation time	12677740729 ps
CPU time	235.48 seconds
Started	Jun 13 12:37:52 PM PDT 24
Finished	Jun 13 12:41:48 PM PDT 24
Peak memory	256844 kb
Host	smart-f13b0ac5-293f-4d82-972c-3049da5dac4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=72618619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.72618619 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_lc_escalation.3757182198
Short name	T39
Test name
Test status
Simulation time	56304774 ps
CPU time	1.4 seconds
Started	Jun 13 12:39:02 PM PDT 24
Finished	Jun 13 12:39:04 PM PDT 24
Peak memory	215604 kb
Host	smart-c56b5e77-7528-4785-b889-ede15c6bdd90
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3757182198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.3757182198 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/34.kmac_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.3302756845
Short name	T96
Test name
Test status
Simulation time	573721658 ps
CPU time	2.84 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	215032 kb
Host	smart-c95aa60c-18e7-453c-8920-9ee22417eed6
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302756845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.3302 756845 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/18.kmac_lc_escalation.1289697078
Short name	T10
Test name
Test status
Simulation time	30643553 ps
CPU time	1.2 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:37:55 PM PDT 24
Peak memory	215708 kb
Host	smart-59a4f517-8ce4-4d83-8d89-09b5832202db
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289697078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.1289697078 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/18.kmac_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_intr_test.391802806
Short name	T101
Test name
Test status
Simulation time	21941716 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206692 kb
Host	smart-50bb51a6-f903-4bab-9ced-2c750020ac30
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391802806 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.391802806 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_intr_test/latest

Test location	/workspace/coverage/default/19.kmac_lc_escalation.4169005004
Short name	T52
Test name
Test status
Simulation time	6393488679 ps
CPU time	37.88 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:38:22 PM PDT 24
Peak memory	232212 kb
Host	smart-ed2f1a24-09cc-4096-a50a-a3344c3869ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4169005004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.4169005004 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/19.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/15.kmac_lc_escalation.4105078469
Short name	T37
Test name
Test status
Simulation time	48935002 ps
CPU time	1.38 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	215596 kb
Host	smart-11186878-196c-4128-805d-4d313e68db8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105078469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.4105078469 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/15.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/47.kmac_lc_escalation.431520366
Short name	T9
Test name
Test status
Simulation time	63516493 ps
CPU time	1.21 seconds
Started	Jun 13 12:41:52 PM PDT 24
Finished	Jun 13 12:41:53 PM PDT 24
Peak memory	215648 kb
Host	smart-65dc2af7-4d8c-465c-986f-e98e54c19540
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=431520366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.431520366 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/47.kmac_lc_escalation/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.1240205216
Short name	T81
Test name
Test status
Simulation time	110314428 ps
CPU time	2.61 seconds
Started	Jun 13 12:34:35 PM PDT 24
Finished	Jun 13 12:34:38 PM PDT 24
Peak memory	215424 kb
Host	smart-45b067ca-b0cb-4e0e-85f8-3cca51965649
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240205216 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac _shadow_reg_errors_with_csr_rw.1240205216 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.1210203266
Short name	T117
Test name
Test status
Simulation time	163272007 ps
CPU time	1.36 seconds
Started	Jun 13 12:34:39 PM PDT 24
Finished	Jun 13 12:34:40 PM PDT 24
Peak memory	215040 kb
Host	smart-423a004b-d12c-4ebd-b53a-1786a9af89cf
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210203266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia l_access.1210203266 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_partial_access/latest

Test location	/workspace/coverage/default/7.kmac_stress_all_with_rand_reset.711803421
Short name	T75
Test name
Test status
Simulation time	28800155669 ps
CPU time	781.87 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 12:50:28 PM PDT 24
Peak memory	284384 kb
Host	smart-f3da6818-6cf2-4ba6-97e3-30e14f380fff
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=711803421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.711803421 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/10.kmac_alert_test.413181700
Short name	T173
Test name
Test status
Simulation time	17850616 ps
CPU time	0.77 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:37:22 PM PDT 24
Peak memory	205148 kb
Host	smart-3b8fda7e-c603-4554-b865-3504cfaf2b10
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413181700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.413181700 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_intr_test.3637331497
Short name	T142
Test name
Test status
Simulation time	34473431 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:19 PM PDT 24
Peak memory	206660 kb
Host	smart-b43340d1-45af-49be-8fe8-03f2907787af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637331497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.3637331497 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_intr_test/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_256.832977344
Short name	T17
Test name
Test status
Simulation time	897196620916 ps
CPU time	4258.82 seconds
Started	Jun 13 12:37:01 PM PDT 24
Finished	Jun 13 01:48:01 PM PDT 24
Peak memory	556448 kb
Host	smart-3ca1460b-9aa2-4f0b-bd0c-e4c4a3305546
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=832977344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.832977344 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.4156338413
Short name	T133
Test name
Test status
Simulation time	247934680 ps
CPU time	5.06 seconds
Started	Jun 13 12:34:53 PM PDT 24
Finished	Jun 13 12:34:59 PM PDT 24
Peak memory	218848 kb
Host	smart-8d8e8eed-97cb-430f-af5c-d692e323d62c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156338413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.41563 38413 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/42.kmac_error.1735200907
Short name	T138
Test name
Test status
Simulation time	18865435428 ps
CPU time	329.74 seconds
Started	Jun 13 12:40:29 PM PDT 24
Finished	Jun 13 12:46:00 PM PDT 24
Peak memory	256820 kb
Host	smart-69a95189-041d-4b31-ba0f-020d3ac0a87b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1735200907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.1735200907 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_224.314617414
Short name	T135
Test name
Test status
Simulation time	146895960007 ps
CPU time	1662.04 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 01:05:08 PM PDT 24
Peak memory	397452 kb
Host	smart-752c6e25-1879-49a3-9686-2b82ddcdcc2b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=314617414 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.314617414 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_entropy_ready_error.3929448430
Short name	T682
Test name
Test status
Simulation time	16891325685 ps
CPU time	53.53 seconds
Started	Jun 13 12:37:27 PM PDT 24
Finished	Jun 13 12:38:22 PM PDT 24
Peak memory	215748 kb
Host	smart-7134fd39-6a45-4fdb-95cf-3acce026cc50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3929448430 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.3929448430 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_stress_all_with_rand_reset.4115254192
Short name	T73
Test name
Test status
Simulation time	155242357265 ps
CPU time	1405.22 seconds
Started	Jun 13 12:37:01 PM PDT 24
Finished	Jun 13 01:00:28 PM PDT 24
Peak memory	354164 kb
Host	smart-cf196815-b2b4-475c-bf27-b8eb4cd4138b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4115254192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.4115254192 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.137761250
Short name	T156
Test name
Test status
Simulation time	397190575 ps
CPU time	2.63 seconds
Started	Jun 13 12:34:31 PM PDT 24
Finished	Jun 13 12:34:34 PM PDT 24
Peak memory	214996 kb
Host	smart-373ab536-3d6b-4d25-9640-428b12745a01
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137761250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.137761 250 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.2636385928
Short name	T97
Test name
Test status
Simulation time	472244472 ps
CPU time	4.8 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:10 PM PDT 24
Peak memory	214984 kb
Host	smart-75a2361f-2b56-4a14-83b4-20ed251acc1b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636385928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.2636 385928 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_intr_test.133399930
Short name	T1135
Test name
Test status
Simulation time	20933693 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:07 PM PDT 24
Finished	Jun 13 12:35:09 PM PDT 24
Peak memory	206672 kb
Host	smart-0004a6b5-0796-4a12-b6db-cff6c0c4b54e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133399930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.133399930 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3886569218
Short name	T149
Test name
Test status
Simulation time	572044342 ps
CPU time	4.99 seconds
Started	Jun 13 12:35:06 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	206912 kb
Host	smart-e1daff3d-e817-43fe-b2f4-ce85e8f611cf
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886569218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3886 569218 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.778233391
Short name	T152
Test name
Test status
Simulation time	153129964 ps
CPU time	4.17 seconds
Started	Jun 13 12:34:58 PM PDT 24
Finished	Jun 13 12:35:03 PM PDT 24
Peak memory	215036 kb
Host	smart-eacef80c-ec11-4dfb-9ac2-5316bd15166d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778233391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.778233 391 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/2.kmac_app.894212862
Short name	T355
Test name
Test status
Simulation time	29815392434 ps
CPU time	180.26 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 12:40:21 PM PDT 24
Peak memory	238228 kb
Host	smart-14113592-fd2b-4762-9ba0-da733e0b29d8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=894212862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.894212862 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_128.3687618979
Short name	T134
Test name
Test status
Simulation time	1064860956760 ps
CPU time	5117.01 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 02:03:06 PM PDT 24
Peak memory	645632 kb
Host	smart-77014cf4-9692-4c21-8662-86212a6d2fa4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3687618979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.3687618979 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.644765631
Short name	T102
Test name
Test status
Simulation time	193563981 ps
CPU time	2.45 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215412 kb
Host	smart-afdad3ca-f722-4846-bd81-d33c37df357a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644765631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.64476 5631 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_intg_err/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_256.1612737922
Short name	T16
Test name
Test status
Simulation time	36118301127 ps
CPU time	1445.73 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 01:02:02 PM PDT 24
Peak memory	373524 kb
Host	smart-bfc6e372-f048-4903-a112-35f00ec57d9c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1612737922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.1612737922 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.707231322
Short name	T1105
Test name
Test status
Simulation time	80072953 ps
CPU time	4.39 seconds
Started	Jun 13 12:34:49 PM PDT 24
Finished	Jun 13 12:34:54 PM PDT 24
Peak memory	215024 kb
Host	smart-9e7a6a9e-9e51-42ec-95c3-525d0e27117a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707231322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.70723132 2 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.3139597100
Short name	T1096
Test name
Test status
Simulation time	292411745 ps
CPU time	14.9 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:57 PM PDT 24
Peak memory	206848 kb
Host	smart-82a72781-352a-4892-a328-2a8db9ba8eba
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139597100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3139597 100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.3032333291
Short name	T129
Test name
Test status
Simulation time	35272414 ps
CPU time	0.95 seconds
Started	Jun 13 12:34:30 PM PDT 24
Finished	Jun 13 12:34:32 PM PDT 24
Peak memory	206600 kb
Host	smart-698822a6-e09c-435d-8764-9f3e884eb311
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032333291 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3032333 291 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.408615627
Short name	T1192
Test name
Test status
Simulation time	174196185 ps
CPU time	1.46 seconds
Started	Jun 13 12:34:26 PM PDT 24
Finished	Jun 13 12:34:28 PM PDT 24
Peak memory	222812 kb
Host	smart-58f67499-ed05-4e27-a54f-ada0082fd7cf
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408615627 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.408615627 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_csr_rw.3334856658
Short name	T131
Test name
Test status
Simulation time	25715794 ps
CPU time	1.02 seconds
Started	Jun 13 12:34:24 PM PDT 24
Finished	Jun 13 12:34:25 PM PDT 24
Peak memory	214796 kb
Host	smart-1b296880-eb0e-4e8a-8b43-3b41447166fa
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334856658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.3334856658 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_intr_test.1109387045
Short name	T1147
Test name
Test status
Simulation time	30108051 ps
CPU time	0.73 seconds
Started	Jun 13 12:34:29 PM PDT 24
Finished	Jun 13 12:34:30 PM PDT 24
Peak memory	206580 kb
Host	smart-6ceb0db7-5442-4d05-9f09-379f0e839b98
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109387045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.1109387045 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_mem_walk.2942769643
Short name	T1098
Test name
Test status
Simulation time	51651255 ps
CPU time	0.7 seconds
Started	Jun 13 12:34:37 PM PDT 24
Finished	Jun 13 12:34:38 PM PDT 24
Peak memory	206596 kb
Host	smart-8bc9edbd-7b47-4709-866b-92eb6fde4f18
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942769643 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2942769643 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.3630597528
Short name	T1093
Test name
Test status
Simulation time	177213634 ps
CPU time	1.49 seconds
Started	Jun 13 12:34:34 PM PDT 24
Finished	Jun 13 12:34:35 PM PDT 24
Peak memory	215036 kb
Host	smart-fb7a1f20-da9d-4725-bd6e-bbf891a5d200
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630597528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr _outstanding.3630597528 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.3503644913
Short name	T88
Test name
Test status
Simulation time	105370621 ps
CPU time	1.03 seconds
Started	Jun 13 12:34:38 PM PDT 24
Finished	Jun 13 12:34:40 PM PDT 24
Peak memory	207260 kb
Host	smart-1b7d5c02-e1b3-4a45-8ae0-ea69e2df0201
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503644913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_ errors.3503644913 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.kmac_tl_errors.558226957
Short name	T1124
Test name
Test status
Simulation time	83525984 ps
CPU time	1.7 seconds
Started	Jun 13 12:34:35 PM PDT 24
Finished	Jun 13 12:34:37 PM PDT 24
Peak memory	215036 kb
Host	smart-d7f2936e-bbb3-45dc-a032-bd2eec4a84f4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558226957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.558226957 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.606035166
Short name	T1137
Test name
Test status
Simulation time	964802513 ps
CPU time	9.43 seconds
Started	Jun 13 12:34:36 PM PDT 24
Finished	Jun 13 12:34:47 PM PDT 24
Peak memory	206824 kb
Host	smart-01cd579e-ac73-4d8e-8350-f364c0e210df
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606035166 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.60603516 6 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3861112848
Short name	T1199
Test name
Test status
Simulation time	219657377 ps
CPU time	7.79 seconds
Started	Jun 13 12:34:34 PM PDT 24
Finished	Jun 13 12:34:42 PM PDT 24
Peak memory	206840 kb
Host	smart-abb3c0cb-8f47-47aa-9807-aa75b16d9162
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861112848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3861112 848 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1915826022
Short name	T1107
Test name
Test status
Simulation time	112512953 ps
CPU time	0.88 seconds
Started	Jun 13 12:34:36 PM PDT 24
Finished	Jun 13 12:34:37 PM PDT 24
Peak memory	206576 kb
Host	smart-25726434-80a6-4a5c-9f70-45c35ffff8fd
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915826022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1915826 022 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.2818648540
Short name	T1167
Test name
Test status
Simulation time	284920015 ps
CPU time	2.17 seconds
Started	Jun 13 12:34:35 PM PDT 24
Finished	Jun 13 12:34:38 PM PDT 24
Peak memory	223208 kb
Host	smart-5ce3c15d-6685-45cf-b932-75a7aec7a536
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818648540 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.2818648540 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_csr_rw.3768031476
Short name	T1166
Test name
Test status
Simulation time	31863242 ps
CPU time	1.17 seconds
Started	Jun 13 12:34:35 PM PDT 24
Finished	Jun 13 12:34:36 PM PDT 24
Peak memory	206792 kb
Host	smart-5ad1f888-4d58-4d1d-96de-138718815c4d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768031476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.3768031476 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_intr_test.3534081998
Short name	T1248
Test name
Test status
Simulation time	16314476 ps
CPU time	0.77 seconds
Started	Jun 13 12:34:33 PM PDT 24
Finished	Jun 13 12:34:34 PM PDT 24
Peak memory	206596 kb
Host	smart-919102e3-9054-49eb-af02-83dab29ba0ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534081998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.3534081998 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.3131396911
Short name	T116
Test name
Test status
Simulation time	97844122 ps
CPU time	1.15 seconds
Started	Jun 13 12:34:34 PM PDT 24
Finished	Jun 13 12:34:35 PM PDT 24
Peak memory	214988 kb
Host	smart-15955aab-fb5a-4e80-9d89-4422869d7e41
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131396911 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia l_access.3131396911 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_mem_walk.2135241963
Short name	T1196
Test name
Test status
Simulation time	39544897 ps
CPU time	0.75 seconds
Started	Jun 13 12:34:24 PM PDT 24
Finished	Jun 13 12:34:25 PM PDT 24
Peak memory	206936 kb
Host	smart-1ca30345-b0c2-4a91-9168-0d52fed7620d
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135241963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.2135241963 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.1508641532
Short name	T1205
Test name
Test status
Simulation time	50190704 ps
CPU time	1.53 seconds
Started	Jun 13 12:34:31 PM PDT 24
Finished	Jun 13 12:34:33 PM PDT 24
Peak memory	215568 kb
Host	smart-aa00b0d5-aa13-4ea1-8dbe-1eaac4b96be9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508641532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr _outstanding.1508641532 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.3566552478
Short name	T82
Test name
Test status
Simulation time	28789979 ps
CPU time	0.92 seconds
Started	Jun 13 12:34:40 PM PDT 24
Finished	Jun 13 12:34:41 PM PDT 24
Peak memory	206736 kb
Host	smart-e46e9889-1f45-43c4-9dd2-132225dd950c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566552478 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_ errors.3566552478 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.896441447
Short name	T83
Test name
Test status
Simulation time	240699107 ps
CPU time	2.89 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:45 PM PDT 24
Peak memory	215352 kb
Host	smart-f72e0396-046f-4e35-8c56-a80903560492
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896441447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_ shadow_reg_errors_with_csr_rw.896441447 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_errors.454053682
Short name	T1204
Test name
Test status
Simulation time	106228024 ps
CPU time	2.74 seconds
Started	Jun 13 12:34:36 PM PDT 24
Finished	Jun 13 12:34:39 PM PDT 24
Peak memory	215048 kb
Host	smart-e15eec12-b345-405e-a739-87d9a8361468
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454053682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.454053682 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.1362613644
Short name	T148
Test name
Test status
Simulation time	107906977 ps
CPU time	2.56 seconds
Started	Jun 13 12:34:31 PM PDT 24
Finished	Jun 13 12:34:34 PM PDT 24
Peak memory	206852 kb
Host	smart-a9ab2fa9-c0bc-4956-b612-4ea8d1d5188d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362613644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.13626 13644 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.3250343828
Short name	T1226
Test name
Test status
Simulation time	55127839 ps
CPU time	1.8 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	215648 kb
Host	smart-d13010f3-9f6f-4ceb-b714-d9a6cf6e96cb
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250343828 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.3250343828 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_csr_rw.1292310222
Short name	T1130
Test name
Test status
Simulation time	20809336 ps
CPU time	0.97 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:05 PM PDT 24
Peak memory	206588 kb
Host	smart-9813f9be-7071-4c0f-92fb-8a90d996c015
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292310222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.1292310222 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_intr_test.3957265399
Short name	T1171
Test name
Test status
Simulation time	14036748 ps
CPU time	0.74 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	206644 kb
Host	smart-8c3f1660-a11c-4ebc-8491-9a71586f768f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957265399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.3957265399 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.2600453272
Short name	T1094
Test name
Test status
Simulation time	201865754 ps
CPU time	1.62 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	215020 kb
Host	smart-9cd3496d-cff2-4e5a-916b-62833c3d7325
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600453272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_cs r_outstanding.2600453272 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.2230974333
Short name	T1133
Test name
Test status
Simulation time	25287189 ps
CPU time	1.04 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:06 PM PDT 24
Peak memory	215544 kb
Host	smart-f81dd62e-2632-418c-8c8d-da517d89e518
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230974333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg _errors.2230974333 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2151846937
Short name	T1175
Test name
Test status
Simulation time	174931474 ps
CPU time	1.48 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	215108 kb
Host	smart-76329189-6d82-424b-a1b3-37fe8ddfcb00
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151846937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma c_shadow_reg_errors_with_csr_rw.2151846937 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_errors.2200077666
Short name	T1218
Test name
Test status
Simulation time	80303120 ps
CPU time	2.63 seconds
Started	Jun 13 12:35:07 PM PDT 24
Finished	Jun 13 12:35:10 PM PDT 24
Peak memory	215152 kb
Host	smart-8c1d59b0-3d4c-4594-9e5e-69d48422c7b0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200077666 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2200077666 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.2440972851
Short name	T1230
Test name
Test status
Simulation time	193245471 ps
CPU time	4.37 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:09 PM PDT 24
Peak memory	215028 kb
Host	smart-7e74c84c-fcc3-4c3c-88b6-8126a3add725
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440972851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.2440 972851 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.1285369069
Short name	T1225
Test name
Test status
Simulation time	119580466 ps
CPU time	2.26 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	216900 kb
Host	smart-35b3564f-1d7f-45f6-b082-a864bbb436fd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285369069 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.1285369069 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_csr_rw.2396665063
Short name	T1152
Test name
Test status
Simulation time	94725196 ps
CPU time	1.12 seconds
Started	Jun 13 12:35:07 PM PDT 24
Finished	Jun 13 12:35:09 PM PDT 24
Peak memory	206752 kb
Host	smart-3ed971a6-41b0-4882-9437-be51d4f13e02
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396665063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.2396665063 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_intr_test.485169062
Short name	T1156
Test name
Test status
Simulation time	15293022 ps
CPU time	0.84 seconds
Started	Jun 13 12:35:06 PM PDT 24
Finished	Jun 13 12:35:08 PM PDT 24
Peak memory	206692 kb
Host	smart-20cd1755-bd70-47a8-a452-45e7caad87a3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485169062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.485169062 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.790773443
Short name	T1163
Test name
Test status
Simulation time	74304072 ps
CPU time	2.28 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	215104 kb
Host	smart-d838f551-91d1-4b55-95f0-2eb9ccdf5008
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790773443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr _outstanding.790773443 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2707268088
Short name	T1153
Test name
Test status
Simulation time	26944950 ps
CPU time	1.14 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	215496 kb
Host	smart-d4ee14c4-c91b-4372-a109-6cea78e3a8e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707268088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg _errors.2707268088 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_errors.2054969305
Short name	T1232
Test name
Test status
Simulation time	139523473 ps
CPU time	2.15 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	215028 kb
Host	smart-3f88e29c-46e7-4de6-b48f-8ace761ee241
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054969305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2054969305 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.2866585049
Short name	T153
Test name
Test status
Simulation time	111354882 ps
CPU time	2.78 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:08 PM PDT 24
Peak memory	215048 kb
Host	smart-a8d8e306-7aba-4ff7-978c-b0114b01adba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866585049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2866 585049 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.451352254
Short name	T1178
Test name
Test status
Simulation time	75360145 ps
CPU time	1.49 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:10 PM PDT 24
Peak memory	215228 kb
Host	smart-b14e94c7-e666-41db-9009-a738322571d6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451352254 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.451352254 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_csr_rw.3621652100
Short name	T1095
Test name
Test status
Simulation time	28594858 ps
CPU time	1.13 seconds
Started	Jun 13 12:35:03 PM PDT 24
Finished	Jun 13 12:35:05 PM PDT 24
Peak memory	215004 kb
Host	smart-7127f77d-4981-420a-a1ca-0f323e330edc
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621652100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.3621652100 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_intr_test.511538821
Short name	T1198
Test name
Test status
Simulation time	45921825 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:06 PM PDT 24
Finished	Jun 13 12:35:08 PM PDT 24
Peak memory	206636 kb
Host	smart-90cd0590-3860-40a4-8974-7624eba71e47
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511538821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.511538821 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.2348019142
Short name	T1215
Test name
Test status
Simulation time	28327228 ps
CPU time	1.55 seconds
Started	Jun 13 12:35:03 PM PDT 24
Finished	Jun 13 12:35:06 PM PDT 24
Peak memory	215156 kb
Host	smart-63adad81-70b9-4551-86d7-4f1129e189ef
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348019142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs r_outstanding.2348019142 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors.2318860210
Short name	T89
Test name
Test status
Simulation time	107101186 ps
CPU time	1.06 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:06 PM PDT 24
Peak memory	215512 kb
Host	smart-9085ecd2-60ac-4e0c-83b7-a223c0ebc9e9
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318860210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg _errors.2318860210 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1368407559
Short name	T1138
Test name
Test status
Simulation time	63954915 ps
CPU time	1.82 seconds
Started	Jun 13 12:35:03 PM PDT 24
Finished	Jun 13 12:35:05 PM PDT 24
Peak memory	215408 kb
Host	smart-aaf5d767-d3bc-4957-9886-d403d49fd64a
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368407559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma c_shadow_reg_errors_with_csr_rw.1368407559 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.kmac_tl_errors.227211266
Short name	T1126
Test name
Test status
Simulation time	23590631 ps
CPU time	1.41 seconds
Started	Jun 13 12:35:05 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	215084 kb
Host	smart-93e5a087-111d-4792-94fd-b90fd074d175
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227211266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.227211266 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2457509839
Short name	T1100
Test name
Test status
Simulation time	84912628 ps
CPU time	2.52 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	223316 kb
Host	smart-2824ae80-9019-4cfa-b25d-88b0629543f2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457509839 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2457509839 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_csr_rw.2755279786
Short name	T1182
Test name
Test status
Simulation time	85202379 ps
CPU time	1.14 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	206840 kb
Host	smart-c283d5a7-c333-45ce-a931-4d20c95d0904
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755279786 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.2755279786 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_intr_test.330507620
Short name	T144
Test name
Test status
Simulation time	12933602 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	206668 kb
Host	smart-4cf35d72-3d88-4a13-9595-eec0c663e09c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330507620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.330507620 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.4278173732
Short name	T1238
Test name
Test status
Simulation time	25814589 ps
CPU time	1.51 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	215424 kb
Host	smart-7a63645c-b32a-4f3f-b487-a6d0e7f7a63a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278173732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_cs r_outstanding.4278173732 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3732452801
Short name	T1209
Test name
Test status
Simulation time	104948281 ps
CPU time	1.43 seconds
Started	Jun 13 12:35:07 PM PDT 24
Finished	Jun 13 12:35:09 PM PDT 24
Peak memory	215396 kb
Host	smart-65fe219a-928c-4bb4-81ee-a2c1f506d0f8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732452801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg _errors.3732452801 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.3821636020
Short name	T157
Test name
Test status
Simulation time	90950698 ps
CPU time	2.59 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	223644 kb
Host	smart-a2e6a3ac-45f6-4593-a9ee-d43cd063cf5c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821636020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma c_shadow_reg_errors_with_csr_rw.3821636020 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_errors.481779413
Short name	T1122
Test name
Test status
Simulation time	29642934 ps
CPU time	1.78 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215036 kb
Host	smart-3a2c594f-e7bf-425d-ad3c-884280d47cd3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481779413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.481779413 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.4123018428
Short name	T151
Test name
Test status
Simulation time	100401731 ps
CPU time	2.67 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:15 PM PDT 24
Peak memory	217472 kb
Host	smart-e4c41a38-7438-449f-b868-db40938318c1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123018428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.4123 018428 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.2245797138
Short name	T1240
Test name
Test status
Simulation time	38088065 ps
CPU time	1.58 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	222664 kb
Host	smart-8eee2687-e9bf-4462-a67b-f6c38cc28e4d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245797138 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.2245797138 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_csr_rw.3642565691
Short name	T1140
Test name
Test status
Simulation time	30759572 ps
CPU time	1.14 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	206792 kb
Host	smart-d188941c-89d5-418b-ab0a-3556b9fec007
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642565691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.3642565691 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.924469006
Short name	T1155
Test name
Test status
Simulation time	92628299 ps
CPU time	2.39 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	215060 kb
Host	smart-823847b3-29cf-4d99-8187-fb7e01808781
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924469006 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_csr _outstanding.924469006 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.1847217968
Short name	T1239
Test name
Test status
Simulation time	104512892 ps
CPU time	1.1 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:12 PM PDT 24
Peak memory	215440 kb
Host	smart-7208bc65-e18d-453d-aaa8-c8e52081e9f7
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847217968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg _errors.1847217968 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.1955098710
Short name	T1170
Test name
Test status
Simulation time	373906008 ps
CPU time	2.41 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	215472 kb
Host	smart-2a29b8cb-31d0-4aae-b2c4-28cf11037a85
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955098710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kma c_shadow_reg_errors_with_csr_rw.1955098710 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.kmac_tl_errors.1708995636
Short name	T1186
Test name
Test status
Simulation time	85394165 ps
CPU time	1.54 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215040 kb
Host	smart-9cde94d0-51ed-41ae-93a6-d388c0331238
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708995636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.1708995636 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.3123459620
Short name	T1109
Test name
Test status
Simulation time	78268826 ps
CPU time	1.66 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	223260 kb
Host	smart-d0632b9d-f906-4074-85e0-90aed57e959a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123459620 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.3123459620 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_csr_rw.2891816436
Short name	T1247
Test name
Test status
Simulation time	97266569 ps
CPU time	1.13 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	206848 kb
Host	smart-35df3563-d8fc-4a88-b116-f0be29b256e2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891816436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.2891816436 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_intr_test.2502270045
Short name	T1200
Test name
Test status
Simulation time	30624666 ps
CPU time	0.73 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	206672 kb
Host	smart-c012e7f5-3e33-4561-bc35-f4c5c633a57b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502270045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.2502270045 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.1879173982
Short name	T1110
Test name
Test status
Simulation time	97359975 ps
CPU time	2.81 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	215576 kb
Host	smart-26710908-ca2c-49ca-9244-c3c11bca1b58
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879173982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs r_outstanding.1879173982 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.2295691118
Short name	T1193
Test name
Test status
Simulation time	33478895 ps
CPU time	1.02 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	215396 kb
Host	smart-161ac31e-d557-40f7-b2ac-aabdaba44c77
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295691118 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg _errors.2295691118 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.1028737079
Short name	T1221
Test name
Test status
Simulation time	353225691 ps
CPU time	1.93 seconds
Started	Jun 13 12:35:08 PM PDT 24
Finished	Jun 13 12:35:11 PM PDT 24
Peak memory	215376 kb
Host	smart-9670a498-1584-4af4-b8b8-3befd6216559
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028737079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma c_shadow_reg_errors_with_csr_rw.1028737079 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.kmac_tl_errors.224873820
Short name	T1160
Test name
Test status
Simulation time	59400361 ps
CPU time	1.75 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215064 kb
Host	smart-29d8d1a8-43ff-4007-9f81-0ad54a5a6c64
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224873820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.224873820 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.2571422115
Short name	T1202
Test name
Test status
Simulation time	119629413 ps
CPU time	2.26 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	216392 kb
Host	smart-09db5233-7019-4284-92af-10998c7355d1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571422115 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.2571422115 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_csr_rw.392845662
Short name	T1161
Test name
Test status
Simulation time	22712609 ps
CPU time	0.91 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	206656 kb
Host	smart-dc60358a-effe-4b38-a1fc-ded53e671055
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392845662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.392845662 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_intr_test.4188894184
Short name	T1101
Test name
Test status
Simulation time	21259965 ps
CPU time	0.77 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	206684 kb
Host	smart-b9ab60bb-b5ba-4b9e-8a6a-c825a6a2cebf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188894184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.4188894184 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.1705033896
Short name	T1177
Test name
Test status
Simulation time	42464731 ps
CPU time	1.47 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	215084 kb
Host	smart-3237a89e-45c3-40d3-b79c-ddc8eeaae5c5
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705033896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_cs r_outstanding.1705033896 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.51516699
Short name	T1173
Test name
Test status
Simulation time	23833273 ps
CPU time	1.08 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215136 kb
Host	smart-5636819d-0fee-4f5a-a2ce-7d778d8da0fb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51516699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_e rrors.51516699 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.2486907392
Short name	T1243
Test name
Test status
Simulation time	41262723 ps
CPU time	2.28 seconds
Started	Jun 13 12:35:09 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215476 kb
Host	smart-d24e0198-f049-4dc5-9566-bf70dc88121c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486907392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma c_shadow_reg_errors_with_csr_rw.2486907392 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.kmac_tl_errors.2040590885
Short name	T1246
Test name
Test status
Simulation time	38506590 ps
CPU time	2.29 seconds
Started	Jun 13 12:35:11 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	215076 kb
Host	smart-de575dd4-8d36-4644-bb9d-c52c874a5e40
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040590885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.2040590885 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.408369585
Short name	T1183
Test name
Test status
Simulation time	83852968 ps
CPU time	1.54 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:19 PM PDT 24
Peak memory	215060 kb
Host	smart-18c2f44a-c8bb-4c05-b285-7c1db8aa2d99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408369585 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.408369585 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_csr_rw.1686494854
Short name	T1227
Test name
Test status
Simulation time	15603228 ps
CPU time	0.9 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:19 PM PDT 24
Peak memory	206660 kb
Host	smart-5f77b06d-0cdf-4698-be89-e1bcf7696234
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686494854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.1686494854 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.2611312495
Short name	T1194
Test name
Test status
Simulation time	40518573 ps
CPU time	2.04 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	215176 kb
Host	smart-7e8d98d9-11ae-4ff8-84f6-1a1665af1153
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611312495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs r_outstanding.2611312495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.499156620
Short name	T1229
Test name
Test status
Simulation time	103958372 ps
CPU time	1.2 seconds
Started	Jun 13 12:35:10 PM PDT 24
Finished	Jun 13 12:35:13 PM PDT 24
Peak memory	215480 kb
Host	smart-9b66e912-92da-4762-a1e5-b4b33e2b0559
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499156620 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_ errors.499156620 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_errors.3975074952
Short name	T1237
Test name
Test status
Simulation time	60369619 ps
CPU time	1.95 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	215072 kb
Host	smart-6df5f92e-8be5-4a38-a523-6bf2ca560bfb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975074952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.3975074952 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.3253936634
Short name	T155
Test name
Test status
Simulation time	240304913 ps
CPU time	4.65 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	214988 kb
Host	smart-11aac7f0-04fd-4ce4-b278-967997e9e573
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253936634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.3253 936634 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.924153734
Short name	T126
Test name
Test status
Simulation time	159940304 ps
CPU time	2.46 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	216244 kb
Host	smart-bcb8e783-38ed-480c-a505-28813cfd5d2b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924153734 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.924153734 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_csr_rw.1348286730
Short name	T1174
Test name
Test status
Simulation time	34491966 ps
CPU time	1.2 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	206832 kb
Host	smart-9a173ab5-09dc-4d23-a549-b31d131bd066
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348286730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.1348286730 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_intr_test.2785864848
Short name	T1252
Test name
Test status
Simulation time	25971545 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:12 PM PDT 24
Finished	Jun 13 12:35:14 PM PDT 24
Peak memory	206688 kb
Host	smart-9647bf53-903a-4ad7-a28e-400e26ebc28a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785864848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.2785864848 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2779992868
Short name	T1125
Test name
Test status
Simulation time	131877123 ps
CPU time	2.73 seconds
Started	Jun 13 12:35:21 PM PDT 24
Finished	Jun 13 12:35:25 PM PDT 24
Peak memory	215152 kb
Host	smart-4c100861-79c1-412f-b139-7f0089da8818
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779992868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs r_outstanding.2779992868 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.4248894140
Short name	T85
Test name
Test status
Simulation time	73687829 ps
CPU time	1.31 seconds
Started	Jun 13 12:35:15 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	215488 kb
Host	smart-02420796-ae28-415f-afd0-a5de4c429ef4
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248894140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg _errors.4248894140 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.1116859098
Short name	T1212
Test name
Test status
Simulation time	118373203 ps
CPU time	2 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	215496 kb
Host	smart-b75f5d07-aa05-4323-890c-04a91688f0d0
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116859098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma c_shadow_reg_errors_with_csr_rw.1116859098 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_errors.999150738
Short name	T1236
Test name
Test status
Simulation time	105424236 ps
CPU time	2.06 seconds
Started	Jun 13 12:35:15 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	215028 kb
Host	smart-569903d6-7736-4bd9-8baf-ea73db232038
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999150738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.999150738 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.4135610687
Short name	T1219
Test name
Test status
Simulation time	722728501 ps
CPU time	4.93 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:24 PM PDT 24
Peak memory	215064 kb
Host	smart-e44dfb82-5c94-4e6a-a7db-7e959d572ecb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135610687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.4135 610687 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.385114172
Short name	T1217
Test name
Test status
Simulation time	463912809 ps
CPU time	1.75 seconds
Started	Jun 13 12:35:15 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	223224 kb
Host	smart-74e2eb5d-7f74-4adb-8d10-5f6588608fb2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385114172 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.385114172 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_csr_rw.468949638
Short name	T1169
Test name
Test status
Simulation time	15962132 ps
CPU time	1.1 seconds
Started	Jun 13 12:35:19 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	214964 kb
Host	smart-95cd25fb-0cbd-4687-b8ce-f209b650ca4a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468949638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.468949638 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.1986885099
Short name	T1208
Test name
Test status
Simulation time	97122623 ps
CPU time	1.6 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:19 PM PDT 24
Peak memory	215228 kb
Host	smart-36857488-b58a-464b-a152-c85541176f44
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986885099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_cs r_outstanding.1986885099 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.1288985098
Short name	T1190
Test name
Test status
Simulation time	71161463 ps
CPU time	0.95 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	206744 kb
Host	smart-311d5f9b-b430-4d52-892f-7e5211fa2f72
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288985098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg _errors.1288985098 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.2133592333
Short name	T1222
Test name
Test status
Simulation time	67322675 ps
CPU time	1.8 seconds
Started	Jun 13 12:35:15 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	206948 kb
Host	smart-73d7bae2-0263-4e95-b429-8d371e1566b8
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133592333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kma c_shadow_reg_errors_with_csr_rw.2133592333 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_errors.553865107
Short name	T1250
Test name
Test status
Simulation time	532662741 ps
CPU time	3.05 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:21 PM PDT 24
Peak memory	215100 kb
Host	smart-17fb7a8e-0e36-4b29-817e-899257aa0356
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553865107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.553865107 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.2990890610
Short name	T1210
Test name
Test status
Simulation time	256281599 ps
CPU time	2.99 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	207196 kb
Host	smart-29e9486a-bc11-4331-a7c9-38f035e1e532
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990890610 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2990 890610 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.677212741
Short name	T1181
Test name
Test status
Simulation time	1738870435 ps
CPU time	5.21 seconds
Started	Jun 13 12:34:40 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	206868 kb
Host	smart-3e1f7145-962c-4ed4-a9b2-e5a7315769a8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677212741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.67721274 1 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2072489075
Short name	T1116
Test name
Test status
Simulation time	1662043074 ps
CPU time	15.29 seconds
Started	Jun 13 12:34:32 PM PDT 24
Finished	Jun 13 12:34:48 PM PDT 24
Peak memory	206848 kb
Host	smart-70b9c589-6ee8-4c9f-91c4-d018519d19fb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072489075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2072489 075 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.3770325730
Short name	T1165
Test name
Test status
Simulation time	84345568 ps
CPU time	0.98 seconds
Started	Jun 13 12:34:43 PM PDT 24
Finished	Jun 13 12:34:44 PM PDT 24
Peak memory	206672 kb
Host	smart-795fd7d3-acd4-4678-b57f-937e5f2fb1ca
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770325730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.3770325 730 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.346550574
Short name	T1235
Test name
Test status
Simulation time	293935412 ps
CPU time	2.27 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:45 PM PDT 24
Peak memory	223228 kb
Host	smart-dd7508a3-b313-4751-8788-fdd4d305059e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346550574 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.346550574 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_csr_rw.3703449562
Short name	T1149
Test name
Test status
Simulation time	148295511 ps
CPU time	1.03 seconds
Started	Jun 13 12:34:37 PM PDT 24
Finished	Jun 13 12:34:39 PM PDT 24
Peak memory	206880 kb
Host	smart-36b69ca6-1bee-49e7-9c52-146cc1b9d169
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703449562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.3703449562 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_intr_test.2337475892
Short name	T1244
Test name
Test status
Simulation time	20224869 ps
CPU time	0.81 seconds
Started	Jun 13 12:34:42 PM PDT 24
Finished	Jun 13 12:34:44 PM PDT 24
Peak memory	206632 kb
Host	smart-803963f6-4d8f-4ed8-ba82-3c1909e16783
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337475892 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2337475892 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.3901893798
Short name	T118
Test name
Test status
Simulation time	319779946 ps
CPU time	1.28 seconds
Started	Jun 13 12:34:44 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	215088 kb
Host	smart-c0c3fd7a-ccef-45a8-a282-7b85707c05d7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901893798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partia l_access.3901893798 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_mem_walk.1596631036
Short name	T1117
Test name
Test status
Simulation time	10434719 ps
CPU time	0.71 seconds
Started	Jun 13 12:34:31 PM PDT 24
Finished	Jun 13 12:34:33 PM PDT 24
Peak memory	206604 kb
Host	smart-0ab5f47e-af70-42a7-a7e3-88bcb0baeee4
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596631036 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.1596631036 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.869357670
Short name	T124
Test name
Test status
Simulation time	87515873 ps
CPU time	1.48 seconds
Started	Jun 13 12:34:32 PM PDT 24
Finished	Jun 13 12:34:34 PM PDT 24
Peak memory	215348 kb
Host	smart-bf6641d2-3cc3-4d8b-a311-afe7d63a828d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869357670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_ outstanding.869357670 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.2624486141
Short name	T132
Test name
Test status
Simulation time	129970636 ps
CPU time	1.15 seconds
Started	Jun 13 12:34:37 PM PDT 24
Finished	Jun 13 12:34:39 PM PDT 24
Peak memory	215424 kb
Host	smart-dde491b3-8fd6-4cd0-863a-383875b9ea3f
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624486141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_ errors.2624486141 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.68320662
Short name	T1179
Test name
Test status
Simulation time	104876886 ps
CPU time	1.53 seconds
Started	Jun 13 12:34:37 PM PDT 24
Finished	Jun 13 12:34:39 PM PDT 24
Peak memory	215348 kb
Host	smart-15831717-bd87-4e55-b5bf-b60d6cab67e5
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68320662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_s hadow_reg_errors_with_csr_rw.68320662 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_errors.3013027627
Short name	T1106
Test name
Test status
Simulation time	153146201 ps
CPU time	2.18 seconds
Started	Jun 13 12:34:30 PM PDT 24
Finished	Jun 13 12:34:32 PM PDT 24
Peak memory	214996 kb
Host	smart-d1c590e8-5abe-4d8c-9965-17b77653f430
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013027627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3013027627 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.3897140939
Short name	T147
Test name
Test status
Simulation time	763376248 ps
CPU time	4.53 seconds
Started	Jun 13 12:34:35 PM PDT 24
Finished	Jun 13 12:34:40 PM PDT 24
Peak memory	206792 kb
Host	smart-ef4606ca-c6af-489d-a60a-6046132744f5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897140939 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.38971 40939 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.kmac_intr_test.2455497293
Short name	T1180
Test name
Test status
Simulation time	54170833 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:15 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	206692 kb
Host	smart-5a7c392d-3871-4589-807d-8b4207f3cb05
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455497293 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.2455497293 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.kmac_intr_test.4293008200
Short name	T1207
Test name
Test status
Simulation time	17752382 ps
CPU time	0.77 seconds
Started	Jun 13 12:35:20 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206696 kb
Host	smart-8c319f7c-a2c7-4771-adcf-e19dc434151e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293008200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.4293008200 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.kmac_intr_test.1452477998
Short name	T1119
Test name
Test status
Simulation time	17215274 ps
CPU time	0.9 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206672 kb
Host	smart-95cd2193-6617-4b90-a0db-19f17e1104b9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452477998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.1452477998 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.kmac_intr_test.1757157260
Short name	T1131
Test name
Test status
Simulation time	20277538 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:15 PM PDT 24
Peak memory	206680 kb
Host	smart-cc64ee28-2995-4c61-be06-636924d89d82
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757157260 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.1757157260 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.kmac_intr_test.2772961279
Short name	T1195
Test name
Test status
Simulation time	22516622 ps
CPU time	0.74 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206632 kb
Host	smart-a9595776-cab4-48d2-92e3-a2dd375f08f7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772961279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2772961279 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.kmac_intr_test.3348491788
Short name	T1134
Test name
Test status
Simulation time	17135785 ps
CPU time	0.77 seconds
Started	Jun 13 12:35:21 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206688 kb
Host	smart-2930d380-a5de-4bb1-bbe4-da3e12547d5d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348491788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.3348491788 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.kmac_intr_test.1132456316
Short name	T145
Test name
Test status
Simulation time	14906697 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	206668 kb
Host	smart-e8cc5277-7c3c-49c0-a0c7-9ac53b0ddbb0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132456316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.1132456316 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.kmac_intr_test.306833692
Short name	T1176
Test name
Test status
Simulation time	82646151 ps
CPU time	0.86 seconds
Started	Jun 13 12:35:13 PM PDT 24
Finished	Jun 13 12:35:15 PM PDT 24
Peak memory	206636 kb
Host	smart-07eb6fe4-0f5d-4677-961a-98fce6452a0e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306833692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.306833692 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.kmac_intr_test.3365832181
Short name	T99
Test name
Test status
Simulation time	36114215 ps
CPU time	0.75 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:19 PM PDT 24
Peak memory	206616 kb
Host	smart-c1cafd08-6dfd-4d67-9ea2-d66532524326
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365832181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.3365832181 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.kmac_intr_test.3142151473
Short name	T1159
Test name
Test status
Simulation time	15119897 ps
CPU time	0.8 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206600 kb
Host	smart-2f262d4e-0999-4510-8a8d-423c879d7788
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142151473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.3142151473 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3127927949
Short name	T130
Test name
Test status
Simulation time	546415794 ps
CPU time	9.74 seconds
Started	Jun 13 12:34:45 PM PDT 24
Finished	Jun 13 12:34:55 PM PDT 24
Peak memory	215000 kb
Host	smart-2e63c5b1-b048-474d-8765-b45d892ffff8
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127927949 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3127927 949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.2589952355
Short name	T127
Test name
Test status
Simulation time	1445627933 ps
CPU time	20.5 seconds
Started	Jun 13 12:34:40 PM PDT 24
Finished	Jun 13 12:35:02 PM PDT 24
Peak memory	206792 kb
Host	smart-6b7fe42a-d425-4bdf-ac45-eb6ba586f6eb
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589952355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.2589952 355 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.4264704364
Short name	T1172
Test name
Test status
Simulation time	18786303 ps
CPU time	1.12 seconds
Started	Jun 13 12:34:52 PM PDT 24
Finished	Jun 13 12:34:53 PM PDT 24
Peak memory	206864 kb
Host	smart-00484084-d8f8-4f47-855b-3fc220b1eeaa
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264704364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.4264704 364 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2191284756
Short name	T1127
Test name
Test status
Simulation time	158331817 ps
CPU time	2.36 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:43 PM PDT 24
Peak memory	216028 kb
Host	smart-67480069-d449-417e-8927-8a82e5c717f0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191284756 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2191284756 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_csr_rw.1680411631
Short name	T1251
Test name
Test status
Simulation time	90907076 ps
CPU time	0.87 seconds
Started	Jun 13 12:34:43 PM PDT 24
Finished	Jun 13 12:34:45 PM PDT 24
Peak memory	206640 kb
Host	smart-2d92788f-edf7-4129-a39d-cb6b9506b2e5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680411631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1680411631 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_intr_test.1282427065
Short name	T1206
Test name
Test status
Simulation time	125124915 ps
CPU time	0.79 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:43 PM PDT 24
Peak memory	206668 kb
Host	smart-5f222266-ed81-48d7-a8af-ad9c999338e1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282427065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.1282427065 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.1900836996
Short name	T1121
Test name
Test status
Simulation time	66540953 ps
CPU time	1.48 seconds
Started	Jun 13 12:34:44 PM PDT 24
Finished	Jun 13 12:34:47 PM PDT 24
Peak memory	215032 kb
Host	smart-0c723b81-d153-4bd7-afd5-13278b7bc8c8
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900836996 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia l_access.1900836996 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_mem_walk.1461082803
Short name	T1162
Test name
Test status
Simulation time	13224842 ps
CPU time	0.72 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:42 PM PDT 24
Peak memory	206576 kb
Host	smart-4bda2ade-3aaf-4439-92f5-a801b0c12765
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461082803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.1461082803 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.721760417
Short name	T125
Test name
Test status
Simulation time	62901427 ps
CPU time	1.68 seconds
Started	Jun 13 12:34:42 PM PDT 24
Finished	Jun 13 12:34:45 PM PDT 24
Peak memory	214944 kb
Host	smart-e41deecf-10cd-460f-9292-40ff96500388
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721760417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_ outstanding.721760417 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.1115843747
Short name	T1158
Test name
Test status
Simulation time	50712251 ps
CPU time	1.37 seconds
Started	Jun 13 12:34:41 PM PDT 24
Finished	Jun 13 12:34:43 PM PDT 24
Peak memory	215552 kb
Host	smart-03f464d7-c05c-4893-9aa7-0a45a67f9f74
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115843747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_ errors.1115843747 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.1257719978
Short name	T1203
Test name
Test status
Simulation time	108763011 ps
CPU time	2.69 seconds
Started	Jun 13 12:34:43 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	223552 kb
Host	smart-aea54c1c-3ebd-4e7f-9652-3dad9f094a65
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257719978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac _shadow_reg_errors_with_csr_rw.1257719978 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_errors.3605590927
Short name	T1157
Test name
Test status
Simulation time	115546456 ps
CPU time	2.99 seconds
Started	Jun 13 12:34:42 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	215064 kb
Host	smart-960e46c6-9286-4aa3-a874-96452c98a36b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605590927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.3605590927 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.1220490656
Short name	T1141
Test name
Test status
Simulation time	324666948 ps
CPU time	5.36 seconds
Started	Jun 13 12:34:44 PM PDT 24
Finished	Jun 13 12:34:50 PM PDT 24
Peak memory	206880 kb
Host	smart-de250d3a-5105-4aac-9c30-73d4bb6a2679
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220490656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.12204 90656 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.kmac_intr_test.1936765303
Short name	T1144
Test name
Test status
Simulation time	48918100 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206584 kb
Host	smart-c68a2f4b-2848-45ac-a570-97eb0031d715
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936765303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.1936765303 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.kmac_intr_test.3936243438
Short name	T1197
Test name
Test status
Simulation time	13875909 ps
CPU time	0.73 seconds
Started	Jun 13 12:35:20 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206688 kb
Host	smart-0e9da4cb-ba7e-4738-a2ad-61c704ada411
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936243438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.3936243438 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.kmac_intr_test.2008146777
Short name	T1214
Test name
Test status
Simulation time	19072060 ps
CPU time	0.86 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206668 kb
Host	smart-7a63215f-f979-4c16-b84c-181848ba2ccb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008146777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.2008146777 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.kmac_intr_test.1843761432
Short name	T1233
Test name
Test status
Simulation time	38249605 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:21 PM PDT 24
Peak memory	206764 kb
Host	smart-65805fa9-e959-4250-9729-6f117846ba67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843761432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.1843761432 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.kmac_intr_test.3024906491
Short name	T1249
Test name
Test status
Simulation time	18234899 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:16 PM PDT 24
Peak memory	206628 kb
Host	smart-3e220793-98e5-46dc-861f-2153f4014d51
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024906491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.3024906491 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.kmac_intr_test.4026788354
Short name	T143
Test name
Test status
Simulation time	14816597 ps
CPU time	0.8 seconds
Started	Jun 13 12:35:14 PM PDT 24
Finished	Jun 13 12:35:17 PM PDT 24
Peak memory	206648 kb
Host	smart-840a545a-934e-4f6a-8d7b-add2520a2882
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026788354 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.4026788354 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.kmac_intr_test.965297236
Short name	T1145
Test name
Test status
Simulation time	23352094 ps
CPU time	0.77 seconds
Started	Jun 13 12:35:20 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206764 kb
Host	smart-22f347f8-fd14-46f4-b43b-aa82b31f1a67
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965297236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.965297236 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.kmac_intr_test.1251402261
Short name	T141
Test name
Test status
Simulation time	25333207 ps
CPU time	0.8 seconds
Started	Jun 13 12:35:16 PM PDT 24
Finished	Jun 13 12:35:18 PM PDT 24
Peak memory	206688 kb
Host	smart-6b64a54e-8658-4394-ab0f-513a2a12d4fc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251402261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.1251402261 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.kmac_intr_test.2529120253
Short name	T1114
Test name
Test status
Simulation time	21020706 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206672 kb
Host	smart-e868d483-a1ff-4ac1-b12d-cfc257d99f8a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529120253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2529120253 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.kmac_intr_test.799742995
Short name	T1211
Test name
Test status
Simulation time	14863589 ps
CPU time	0.82 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206664 kb
Host	smart-3b9aa574-fec1-4ed1-ad1a-526cc15039a4
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799742995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.799742995 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.3957138356
Short name	T1143
Test name
Test status
Simulation time	2393537171 ps
CPU time	4.84 seconds
Started	Jun 13 12:34:48 PM PDT 24
Finished	Jun 13 12:34:54 PM PDT 24
Peak memory	206900 kb
Host	smart-5534998a-7663-4872-9014-e4bb0bffb6ed
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957138356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.3957138 356 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.1143100195
Short name	T128
Test name
Test status
Simulation time	1532784163 ps
CPU time	21.12 seconds
Started	Jun 13 12:34:47 PM PDT 24
Finished	Jun 13 12:35:09 PM PDT 24
Peak memory	206768 kb
Host	smart-6950c15c-3aa7-47cb-8fb7-0dbb457a76e1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143100195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.1143100 195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.329907632
Short name	T1132
Test name
Test status
Simulation time	69596401 ps
CPU time	0.95 seconds
Started	Jun 13 12:34:49 PM PDT 24
Finished	Jun 13 12:34:51 PM PDT 24
Peak memory	206548 kb
Host	smart-b644fcda-7034-45cf-bcad-514c46d931b3
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329907632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.32990763 2 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.2034292751
Short name	T1220
Test name
Test status
Simulation time	177851229 ps
CPU time	1.5 seconds
Started	Jun 13 12:34:45 PM PDT 24
Finished	Jun 13 12:34:47 PM PDT 24
Peak memory	215072 kb
Host	smart-685d566d-03b3-48c2-8a4a-7abf6a9ed032
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034292751 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.2034292751 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_csr_rw.2547746858
Short name	T1099
Test name
Test status
Simulation time	35866076 ps
CPU time	0.9 seconds
Started	Jun 13 12:34:43 PM PDT 24
Finished	Jun 13 12:34:44 PM PDT 24
Peak memory	206632 kb
Host	smart-da8fb981-7747-4795-ba5b-c26e0973e274
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547746858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.2547746858 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_intr_test.4283702462
Short name	T1188
Test name
Test status
Simulation time	12714111 ps
CPU time	0.75 seconds
Started	Jun 13 12:34:45 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	206632 kb
Host	smart-a50bd053-51f2-4467-bd69-1c2575fadd64
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283702462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.4283702462 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.1225953466
Short name	T115
Test name
Test status
Simulation time	101810787 ps
CPU time	1.23 seconds
Started	Jun 13 12:34:45 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	214936 kb
Host	smart-232a590b-6202-49e9-abf7-d42b4d63118b
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225953466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia l_access.1225953466 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_mem_walk.3509944577
Short name	T1092
Test name
Test status
Simulation time	12844453 ps
CPU time	0.8 seconds
Started	Jun 13 12:34:49 PM PDT 24
Finished	Jun 13 12:34:51 PM PDT 24
Peak memory	206680 kb
Host	smart-a9a49a9e-92c5-4c72-aa4b-8dd70873eed6
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509944577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.3509944577 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.742872141
Short name	T1228
Test name
Test status
Simulation time	77215215 ps
CPU time	2.25 seconds
Started	Jun 13 12:34:47 PM PDT 24
Finished	Jun 13 12:34:50 PM PDT 24
Peak memory	215220 kb
Host	smart-be2a9a9b-a6d9-422a-9977-a23cd63bf7b9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742872141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_ outstanding.742872141 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.2254898404
Short name	T86
Test name
Test status
Simulation time	98232644 ps
CPU time	1.16 seconds
Started	Jun 13 12:34:37 PM PDT 24
Finished	Jun 13 12:34:38 PM PDT 24
Peak memory	215420 kb
Host	smart-64825ab7-ff08-472e-be4d-76798668cfde
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254898404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_ errors.2254898404 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_errors.639386377
Short name	T1231
Test name
Test status
Simulation time	86438966 ps
CPU time	2.93 seconds
Started	Jun 13 12:34:42 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	215040 kb
Host	smart-4319241f-2034-4439-9548-d2df3aa93585
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639386377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.639386377 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2463982734
Short name	T1216
Test name
Test status
Simulation time	54124559 ps
CPU time	2.46 seconds
Started	Jun 13 12:34:51 PM PDT 24
Finished	Jun 13 12:34:54 PM PDT 24
Peak memory	215152 kb
Host	smart-6675bc00-5ebf-478f-9b28-f64480f6dd8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463982734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.24639 82734 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.kmac_intr_test.2303849997
Short name	T140
Test name
Test status
Simulation time	42608483 ps
CPU time	0.8 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206600 kb
Host	smart-37c441cc-44fd-4640-89b7-ad551b9ec65d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303849997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.2303849997 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.kmac_intr_test.1824354710
Short name	T139
Test name
Test status
Simulation time	21227291 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206668 kb
Host	smart-bf2ec3c9-819a-4669-9c81-fe8c8eec6d54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824354710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.1824354710 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.kmac_intr_test.368805553
Short name	T100
Test name
Test status
Simulation time	16037488 ps
CPU time	0.76 seconds
Started	Jun 13 12:35:20 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206692 kb
Host	smart-791e8e57-025d-431e-9f40-bf9e3c79fef2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368805553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.368805553 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.kmac_intr_test.3780588725
Short name	T1129
Test name
Test status
Simulation time	19644368 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:19 PM PDT 24
Finished	Jun 13 12:35:21 PM PDT 24
Peak memory	206600 kb
Host	smart-72146df2-2fe1-4a6e-b7e0-91b0b36c0d2d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780588725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3780588725 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.kmac_intr_test.844761504
Short name	T1241
Test name
Test status
Simulation time	49675412 ps
CPU time	0.79 seconds
Started	Jun 13 12:35:17 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206668 kb
Host	smart-4f6c3fc2-16ae-4f4c-bfc4-6e81624fb2e9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844761504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.844761504 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.kmac_intr_test.3267485217
Short name	T1223
Test name
Test status
Simulation time	53050459 ps
CPU time	0.77 seconds
Started	Jun 13 12:35:18 PM PDT 24
Finished	Jun 13 12:35:20 PM PDT 24
Peak memory	206688 kb
Host	smart-107fda5c-9319-4bc3-a7ee-b5b0e445184c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267485217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.3267485217 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.kmac_intr_test.3531645256
Short name	T1113
Test name
Test status
Simulation time	15341247 ps
CPU time	0.8 seconds
Started	Jun 13 12:35:21 PM PDT 24
Finished	Jun 13 12:35:22 PM PDT 24
Peak memory	206692 kb
Host	smart-ad6c1c9a-d759-41ec-b6c6-344fd8c378bc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531645256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.3531645256 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.kmac_intr_test.3568607096
Short name	T1187
Test name
Test status
Simulation time	18250892 ps
CPU time	0.82 seconds
Started	Jun 13 12:35:19 PM PDT 24
Finished	Jun 13 12:35:21 PM PDT 24
Peak memory	206732 kb
Host	smart-1efd5284-5f4f-4b65-94b0-e7892c41972e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568607096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.3568607096 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.kmac_intr_test.2459633512
Short name	T1242
Test name
Test status
Simulation time	17044271 ps
CPU time	0.83 seconds
Started	Jun 13 12:35:24 PM PDT 24
Finished	Jun 13 12:35:26 PM PDT 24
Peak memory	206592 kb
Host	smart-3f9e0957-ce49-4f61-a7c7-bb12886fb31c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459633512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.2459633512 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.kmac_intr_test.3918505982
Short name	T1234
Test name
Test status
Simulation time	167522419 ps
CPU time	0.85 seconds
Started	Jun 13 12:35:23 PM PDT 24
Finished	Jun 13 12:35:25 PM PDT 24
Peak memory	206760 kb
Host	smart-3585ed88-a64f-43d0-957f-a5969b6722a2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918505982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.3918505982 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.654007463
Short name	T1164
Test name
Test status
Simulation time	46586607 ps
CPU time	1.69 seconds
Started	Jun 13 12:34:44 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	223228 kb
Host	smart-ee257a9e-ae6c-4869-867b-aebf4a130eb8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654007463 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.654007463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_csr_rw.3001568343
Short name	T1104
Test name
Test status
Simulation time	25653798 ps
CPU time	0.91 seconds
Started	Jun 13 12:34:48 PM PDT 24
Finished	Jun 13 12:34:50 PM PDT 24
Peak memory	206576 kb
Host	smart-6e63deb3-717c-4d47-a1bf-65d8438ab988
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001568343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.3001568343 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_intr_test.3495925489
Short name	T1118
Test name
Test status
Simulation time	17799454 ps
CPU time	0.76 seconds
Started	Jun 13 12:34:46 PM PDT 24
Finished	Jun 13 12:34:47 PM PDT 24
Peak memory	206644 kb
Host	smart-df682827-04f0-4073-8af9-d2d5acbe494f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495925489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3495925489 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.2149204314
Short name	T1139
Test name
Test status
Simulation time	96505147 ps
CPU time	2.64 seconds
Started	Jun 13 12:34:48 PM PDT 24
Finished	Jun 13 12:34:51 PM PDT 24
Peak memory	215092 kb
Host	smart-461aec9c-9ddf-4eaa-b172-5f8320388bfe
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149204314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr _outstanding.2149204314 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.2341973480
Short name	T87
Test name
Test status
Simulation time	25475763 ps
CPU time	1.16 seconds
Started	Jun 13 12:34:44 PM PDT 24
Finished	Jun 13 12:34:46 PM PDT 24
Peak memory	215424 kb
Host	smart-1506d857-d8a2-47b6-9bc9-d499b256638c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341973480 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_ errors.2341973480 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.3890639846
Short name	T1191
Test name
Test status
Simulation time	180064630 ps
CPU time	1.63 seconds
Started	Jun 13 12:34:47 PM PDT 24
Finished	Jun 13 12:34:49 PM PDT 24
Peak memory	215384 kb
Host	smart-58b08fd3-f3d2-4847-be1e-a1276c66499e
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890639846 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac _shadow_reg_errors_with_csr_rw.3890639846 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_errors.4261381574
Short name	T1142
Test name
Test status
Simulation time	120388248 ps
CPU time	3.25 seconds
Started	Jun 13 12:34:45 PM PDT 24
Finished	Jun 13 12:34:49 PM PDT 24
Peak memory	215052 kb
Host	smart-0a632abd-c44d-47e4-839b-74a17b046657
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261381574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.4261381574 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1516837725
Short name	T154
Test name
Test status
Simulation time	513441504 ps
CPU time	4.91 seconds
Started	Jun 13 12:34:53 PM PDT 24
Finished	Jun 13 12:34:58 PM PDT 24
Peak memory	206840 kb
Host	smart-a7aa7f5a-3840-4fe6-ad91-98b00027eea4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516837725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.15168 37725 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.2345109132
Short name	T1151
Test name
Test status
Simulation time	300251750 ps
CPU time	2.31 seconds
Started	Jun 13 12:34:56 PM PDT 24
Finished	Jun 13 12:34:58 PM PDT 24
Peak memory	217560 kb
Host	smart-61703468-8d27-4df7-9b00-8a7829f7a9d8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345109132 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.2345109132 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_csr_rw.3902675566
Short name	T158
Test name
Test status
Simulation time	27117949 ps
CPU time	1.1 seconds
Started	Jun 13 12:34:53 PM PDT 24
Finished	Jun 13 12:34:55 PM PDT 24
Peak memory	206796 kb
Host	smart-b069e521-ac42-4bac-ba66-ece13ad6bf29
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902675566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.3902675566 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_intr_test.3076401372
Short name	T1112
Test name
Test status
Simulation time	28923448 ps
CPU time	0.77 seconds
Started	Jun 13 12:34:56 PM PDT 24
Finished	Jun 13 12:34:58 PM PDT 24
Peak memory	206640 kb
Host	smart-94eae67d-365c-45fe-954c-19543af2b914
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076401372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.3076401372 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.2044072468
Short name	T1102
Test name
Test status
Simulation time	37911047 ps
CPU time	2.13 seconds
Started	Jun 13 12:34:56 PM PDT 24
Finished	Jun 13 12:34:59 PM PDT 24
Peak memory	215044 kb
Host	smart-f6ae6146-33c8-461a-8c56-6e9aaeeeb299
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044072468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr _outstanding.2044072468 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.550811548
Short name	T1224
Test name
Test status
Simulation time	19028018 ps
CPU time	1.08 seconds
Started	Jun 13 12:34:59 PM PDT 24
Finished	Jun 13 12:35:01 PM PDT 24
Peak memory	215420 kb
Host	smart-06e5ce15-7dcf-47c6-8aed-6f4e9be1b44c
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550811548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e rrors.550811548 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.3210237420
Short name	T80
Test name
Test status
Simulation time	113032527 ps
CPU time	1.69 seconds
Started	Jun 13 12:34:50 PM PDT 24
Finished	Jun 13 12:34:52 PM PDT 24
Peak memory	223416 kb
Host	smart-4a72dccb-a46e-41c8-89ea-cf18c8595aaa
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210237420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac _shadow_reg_errors_with_csr_rw.3210237420 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.kmac_tl_errors.3272279594
Short name	T1245
Test name
Test status
Simulation time	101481844 ps
CPU time	2.62 seconds
Started	Jun 13 12:34:52 PM PDT 24
Finished	Jun 13 12:34:55 PM PDT 24
Peak memory	215104 kb
Host	smart-369d3618-4d65-4681-8725-7a0cf15bf06f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272279594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3272279594 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.1313202300
Short name	T1168
Test name
Test status
Simulation time	61420642 ps
CPU time	1.7 seconds
Started	Jun 13 12:34:58 PM PDT 24
Finished	Jun 13 12:35:01 PM PDT 24
Peak memory	215504 kb
Host	smart-5507071f-d59d-4216-98f7-ed8c8c038e99
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313202300 -assert nopostproc +UVM_TESTNAME =kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.1313202300 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_csr_rw.1107960979
Short name	T1097
Test name
Test status
Simulation time	221632289 ps
CPU time	0.98 seconds
Started	Jun 13 12:34:58 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	206688 kb
Host	smart-36caf530-dcb9-4613-b9ac-a893ffc5b4a2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107960979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1107960979 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_intr_test.757188708
Short name	T1111
Test name
Test status
Simulation time	11285610 ps
CPU time	0.76 seconds
Started	Jun 13 12:34:52 PM PDT 24
Finished	Jun 13 12:34:53 PM PDT 24
Peak memory	206660 kb
Host	smart-f4714425-3279-4eca-8d74-069c3cde8c6c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757188708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.757188708 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.3725408391
Short name	T1103
Test name
Test status
Simulation time	84598530 ps
CPU time	1.37 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:06 PM PDT 24
Peak memory	215392 kb
Host	smart-0e4d6846-9db7-484d-9f99-ec53d9551362
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725408391 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr _outstanding.3725408391 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.2569067041
Short name	T1185
Test name
Test status
Simulation time	58646967 ps
CPU time	1.31 seconds
Started	Jun 13 12:34:56 PM PDT 24
Finished	Jun 13 12:34:57 PM PDT 24
Peak memory	215356 kb
Host	smart-6b6e4d94-be92-4b7d-8b44-738f7b79c536
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569067041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_ errors.2569067041 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.2794650681
Short name	T1108
Test name
Test status
Simulation time	74778297 ps
CPU time	2.16 seconds
Started	Jun 13 12:34:49 PM PDT 24
Finished	Jun 13 12:34:52 PM PDT 24
Peak memory	223296 kb
Host	smart-8d6ec49a-d47b-4372-b0da-2c285558e7fb
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794650681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac _shadow_reg_errors_with_csr_rw.2794650681 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_errors.4151673953
Short name	T1189
Test name
Test status
Simulation time	100598259 ps
CPU time	2.58 seconds
Started	Jun 13 12:34:51 PM PDT 24
Finished	Jun 13 12:34:54 PM PDT 24
Peak memory	215076 kb
Host	smart-d28d541b-cf70-4164-9264-ceb46ce4f183
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151673953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.4151673953 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3455018511
Short name	T98
Test name
Test status
Simulation time	648674694 ps
CPU time	2.76 seconds
Started	Jun 13 12:35:00 PM PDT 24
Finished	Jun 13 12:35:03 PM PDT 24
Peak memory	215044 kb
Host	smart-07c097de-39c6-4568-817e-40f76d7a70f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455018511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.34550 18511 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.187991990
Short name	T1253
Test name
Test status
Simulation time	80210590 ps
CPU time	2.3 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:07 PM PDT 24
Peak memory	216772 kb
Host	smart-c910ccea-524f-4599-9b61-5075f2683fe3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187991990 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.187991990 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_csr_rw.3042349893
Short name	T1148
Test name
Test status
Simulation time	27689908 ps
CPU time	1.14 seconds
Started	Jun 13 12:34:57 PM PDT 24
Finished	Jun 13 12:34:59 PM PDT 24
Peak memory	206876 kb
Host	smart-3bddeb30-30aa-4c3f-a67e-9d8a83a6f305
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042349893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.3042349893 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_intr_test.1028917583
Short name	T1136
Test name
Test status
Simulation time	12539965 ps
CPU time	0.75 seconds
Started	Jun 13 12:34:59 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	206632 kb
Host	smart-d706e683-7402-46e5-b7b1-cc3848403b77
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028917583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.1028917583 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.958177014
Short name	T1184
Test name
Test status
Simulation time	46064350 ps
CPU time	1.93 seconds
Started	Jun 13 12:35:04 PM PDT 24
Finished	Jun 13 12:35:06 PM PDT 24
Peak memory	214976 kb
Host	smart-86d7c2f5-493d-4287-bb62-8f9b5d207084
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958177014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr_ outstanding.958177014 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.2364872331
Short name	T1154
Test name
Test status
Simulation time	85609792 ps
CPU time	1.11 seconds
Started	Jun 13 12:34:59 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	215400 kb
Host	smart-a12ae86a-3992-4bf5-994a-37427ae24119
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364872331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_ errors.2364872331 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.2679134685
Short name	T1213
Test name
Test status
Simulation time	321008977 ps
CPU time	2.16 seconds
Started	Jun 13 12:34:56 PM PDT 24
Finished	Jun 13 12:34:59 PM PDT 24
Peak memory	223516 kb
Host	smart-96a5f299-7038-46ae-9e88-f334f367f59d
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679134685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_ SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac _shadow_reg_errors_with_csr_rw.2679134685 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_errors.461297211
Short name	T1120
Test name
Test status
Simulation time	168517652 ps
CPU time	2.32 seconds
Started	Jun 13 12:34:57 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	215008 kb
Host	smart-895d22c0-ea6d-499c-af4c-5b45836b4805
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461297211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.461297211 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.2729761763
Short name	T150
Test name
Test status
Simulation time	208937081 ps
CPU time	4.54 seconds
Started	Jun 13 12:34:57 PM PDT 24
Finished	Jun 13 12:35:02 PM PDT 24
Peak memory	215084 kb
Host	smart-b1eaad7d-d7b1-4c28-97a3-1e47397ae812
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729761763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.27297 61763 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.294858153
Short name	T1128
Test name
Test status
Simulation time	252806772 ps
CPU time	2.23 seconds
Started	Jun 13 12:34:58 PM PDT 24
Finished	Jun 13 12:35:01 PM PDT 24
Peak memory	216508 kb
Host	smart-5a3d06d6-ac71-4782-a639-2cc82416f557
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294858153 -assert nopostproc +UVM_TESTNAME= kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.294858153 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_csr_rw.3015882937
Short name	T1115
Test name
Test status
Simulation time	36327885 ps
CPU time	0.96 seconds
Started	Jun 13 12:34:59 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	206584 kb
Host	smart-681030a0-c6db-44d6-bf2d-4785b5167ab8
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015882937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.3015882937 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_intr_test.4086055746
Short name	T1201
Test name
Test status
Simulation time	28143125 ps
CPU time	0.78 seconds
Started	Jun 13 12:35:00 PM PDT 24
Finished	Jun 13 12:35:01 PM PDT 24
Peak memory	206688 kb
Host	smart-16d65c85-90f3-43f5-af5c-78a39088826b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086055746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.4086055746 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.430642100
Short name	T1150
Test name
Test status
Simulation time	43844618 ps
CPU time	2.26 seconds
Started	Jun 13 12:35:00 PM PDT 24
Finished	Jun 13 12:35:03 PM PDT 24
Peak memory	215044 kb
Host	smart-2516b641-2467-469c-bb6e-5529cb906b3a
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430642100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr_ outstanding.430642100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3603507809
Short name	T1146
Test name
Test status
Simulation time	34539615 ps
CPU time	1.1 seconds
Started	Jun 13 12:34:59 PM PDT 24
Finished	Jun 13 12:35:00 PM PDT 24
Peak memory	215428 kb
Host	smart-a23b3d69-02d9-4048-9bd0-f7baf2c68341
User	root
Command	/workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603507809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_ errors.3603507809 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_shadow_reg_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.kmac_tl_errors.3893482409
Short name	T1123
Test name
Test status
Simulation time	92985834 ps
CPU time	2.7 seconds
Started	Jun 13 12:35:00 PM PDT 24
Finished	Jun 13 12:35:03 PM PDT 24
Peak memory	215028 kb
Host	smart-d88d934d-95e3-4b6b-9251-7b50d126d862
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893482409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3893482409 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_tl_errors/latest

Test location	/workspace/coverage/default/0.kmac_alert_test.453057824
Short name	T914
Test name
Test status
Simulation time	118937527 ps
CPU time	0.86 seconds
Started	Jun 13 12:37:03 PM PDT 24
Finished	Jun 13 12:37:06 PM PDT 24
Peak memory	205196 kb
Host	smart-b2c532b9-0e7f-44d0-9865-65329e26099b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453057824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.453057824 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_alert_test/latest

Test location	/workspace/coverage/default/0.kmac_app.3367355940
Short name	T288
Test name
Test status
Simulation time	47848711559 ps
CPU time	258.08 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:41:12 PM PDT 24
Peak memory	244460 kb
Host	smart-def012a8-c66d-427f-bcf3-f64bb7e55fd4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367355940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3367355940 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_app/latest

Test location	/workspace/coverage/default/0.kmac_app_with_partial_data.3395276110
Short name	T833
Test name
Test status
Simulation time	12941872947 ps
CPU time	169.87 seconds
Started	Jun 13 12:37:02 PM PDT 24
Finished	Jun 13 12:39:53 PM PDT 24
Peak memory	236072 kb
Host	smart-17518d42-2302-4143-9ab4-ac9087b46878
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3395276110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3395276110 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/0.kmac_burst_write.292849372
Short name	T697
Test name
Test status
Simulation time	8390971738 ps
CPU time	180.6 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:40:39 PM PDT 24
Peak memory	225484 kb
Host	smart-08de643f-d34c-40d2-bb80-d372bd702ae7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=292849372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.292849372 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_burst_write/latest

Test location	/workspace/coverage/default/0.kmac_edn_timeout_error.1337850528
Short name	T267
Test name
Test status
Simulation time	2806942476 ps
CPU time	35.16 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:37:28 PM PDT 24
Peak memory	223824 kb
Host	smart-a6c98d0b-de88-4b2b-a30e-f0661016b97d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1337850528 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.1337850528 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_mode_error.3109049107
Short name	T708
Test name
Test status
Simulation time	1381567438 ps
CPU time	25.42 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 12:37:22 PM PDT 24
Peak memory	228028 kb
Host	smart-6e488757-729f-4d5f-a854-3d0194eccd3c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3109049107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3109049107 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_ready_error.3220742884
Short name	T840
Test name
Test status
Simulation time	8376874303 ps
CPU time	74.18 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:38:09 PM PDT 24
Peak memory	215836 kb
Host	smart-92ca7bb0-9403-4c06-8407-fe6c4965cdf8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3220742884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.3220742884 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/0.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/0.kmac_entropy_refresh.4112004287
Short name	T906
Test name
Test status
Simulation time	21856740872 ps
CPU time	85.51 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:38:20 PM PDT 24
Peak memory	228628 kb
Host	smart-93feb3e0-89a7-475a-90dc-806ea6b6ad4f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112004287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4112004287 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/0.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/0.kmac_error.1155010232
Short name	T330
Test name
Test status
Simulation time	12668815836 ps
CPU time	177.34 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:39:50 PM PDT 24
Peak memory	248500 kb
Host	smart-a78546a0-aa02-4ec3-bccf-a59debee560f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1155010232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.1155010232 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_error/latest

Test location	/workspace/coverage/default/0.kmac_key_error.3795778094
Short name	T969
Test name
Test status
Simulation time	250793491 ps
CPU time	1.16 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:36:56 PM PDT 24
Peak memory	206876 kb
Host	smart-98e3479b-9284-4cae-b57e-5178abd5ebfe
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3795778094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3795778094 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_key_error/latest

Test location	/workspace/coverage/default/0.kmac_lc_escalation.3752333465
Short name	T987
Test name
Test status
Simulation time	40754087 ps
CPU time	1.32 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:36:53 PM PDT 24
Peak memory	217816 kb
Host	smart-008eeb56-38db-4f47-a814-feda6d596e42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3752333465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.3752333465 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/0.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/0.kmac_long_msg_and_output.4119130383
Short name	T351
Test name
Test status
Simulation time	68442812524 ps
CPU time	1816.52 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 01:07:09 PM PDT 24
Peak memory	400480 kb
Host	smart-fb3ea7f1-c68b-4a42-8c86-47bec6ac57a4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119130383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_an d_output.4119130383 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/0.kmac_mubi.67137335
Short name	T809
Test name
Test status
Simulation time	64483589202 ps
CPU time	319.65 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:42:13 PM PDT 24
Peak memory	245372 kb
Host	smart-2ac9bc0a-3e6d-46de-8077-70f22c7da16a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=67137335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.67137335 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_mubi/latest

Test location	/workspace/coverage/default/0.kmac_sec_cm.459991443
Short name	T68
Test name
Test status
Simulation time	7224175805 ps
CPU time	31.88 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:37:44 PM PDT 24
Peak memory	241764 kb
Host	smart-9081cfec-f98f-44de-bc42-e20765ee0847
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459991443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.459991443 +enable_masking =0 +sw_key_masked=0
Directory	/workspace/0.kmac_sec_cm/latest

Test location	/workspace/coverage/default/0.kmac_sideload.2085914407
Short name	T949
Test name
Test status
Simulation time	16414414243 ps
CPU time	337.31 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 12:43:09 PM PDT 24
Peak memory	244808 kb
Host	smart-e71622cf-c2c2-4adc-93c9-327b721e10b1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085914407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.2085914407 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_sideload/latest

Test location	/workspace/coverage/default/0.kmac_smoke.2314255225
Short name	T436
Test name
Test status
Simulation time	16069324586 ps
CPU time	69.92 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	222000 kb
Host	smart-32a0bef5-f445-482b-94fb-75395261d5cc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2314255225 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2314255225 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_smoke/latest

Test location	/workspace/coverage/default/0.kmac_stress_all.2203170010
Short name	T328
Test name
Test status
Simulation time	6899735582 ps
CPU time	430.66 seconds
Started	Jun 13 12:37:03 PM PDT 24
Finished	Jun 13 12:44:15 PM PDT 24
Peak memory	305724 kb
Host	smart-999fe972-9e38-4975-9ac7-05df3adf3f37
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2203170010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2203170010 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_stress_all/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac.624429493
Short name	T876
Test name
Test status
Simulation time	660368025 ps
CPU time	4.35 seconds
Started	Jun 13 12:36:48 PM PDT 24
Finished	Jun 13 12:36:55 PM PDT 24
Peak memory	208656 kb
Host	smart-db183e5a-2a44-4153-aae5-c8769eb38296
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624429493 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.kmac_test_vectors_kmac.624429493 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_kmac_xof.3670828289
Short name	T251
Test name
Test status
Simulation time	251274002 ps
CPU time	4.26 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:37:25 PM PDT 24
Peak memory	215796 kb
Host	smart-3246892b-a0af-4956-8098-21a68a1a2ea1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670828289 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3670828289 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_224.1681161462
Short name	T176
Test name
Test status
Simulation time	198511731507 ps
CPU time	1836.64 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 01:08:03 PM PDT 24
Peak memory	377768 kb
Host	smart-0d0932ea-542a-4a2a-91df-d5a4716659e6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1681161462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1681161462 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_256.4175483024
Short name	T228
Test name
Test status
Simulation time	538827122595 ps
CPU time	1805.86 seconds
Started	Jun 13 12:36:50 PM PDT 24
Finished	Jun 13 01:07:00 PM PDT 24
Peak memory	374500 kb
Host	smart-9cf3ee07-4651-4af7-ba27-75445d065318
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4175483024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.4175483024 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_384.3109402731
Short name	T930
Test name
Test status
Simulation time	57883670861 ps
CPU time	1130.09 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:56:01 PM PDT 24
Peak memory	340176 kb
Host	smart-6eae1f22-3921-4370-a254-4c8d474b4355
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3109402731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.3109402731 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_sha3_512.1776563123
Short name	T196
Test name
Test status
Simulation time	50118854227 ps
CPU time	988.76 seconds
Started	Jun 13 12:36:43 PM PDT 24
Finished	Jun 13 12:53:13 PM PDT 24
Peak memory	292424 kb
Host	smart-b933ff83-0f0e-4d3c-9918-fe42bd9b1a6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1776563123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1776563123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_128.341915789
Short name	T107
Test name
Test status
Simulation time	2165099238383 ps
CPU time	4541.56 seconds
Started	Jun 13 12:37:02 PM PDT 24
Finished	Jun 13 01:52:45 PM PDT 24
Peak memory	658104 kb
Host	smart-c8943f1e-a217-4fce-a917-ac00d83f51df
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=341915789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.341915789 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/0.kmac_test_vectors_shake_256.256478261
Short name	T754
Test name
Test status
Simulation time	146521396070 ps
CPU time	3786.24 seconds
Started	Jun 13 12:36:53 PM PDT 24
Finished	Jun 13 01:40:03 PM PDT 24
Peak memory	551584 kb
Host	smart-ed1bef6e-76f7-4902-b1b9-daa357d07778
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=256478261 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.256478261 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/0.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/1.kmac_alert_test.2878647113
Short name	T329
Test name
Test status
Simulation time	39816714 ps
CPU time	0.78 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:37:15 PM PDT 24
Peak memory	205224 kb
Host	smart-30d1c6c9-7cd7-4af8-90a0-8d72ba670d34
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878647113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2878647113 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_alert_test/latest

Test location	/workspace/coverage/default/1.kmac_app.3755848590
Short name	T450
Test name
Test status
Simulation time	3784909107 ps
CPU time	71.81 seconds
Started	Jun 13 12:37:05 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	226812 kb
Host	smart-6feecbd9-03c2-4087-9848-c2ec1a1411c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3755848590 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.3755848590 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_app/latest

Test location	/workspace/coverage/default/1.kmac_app_with_partial_data.2098228765
Short name	T1041
Test name
Test status
Simulation time	15281810580 ps
CPU time	54.8 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 12:37:52 PM PDT 24
Peak memory	223976 kb
Host	smart-beb2341b-2657-4a66-b3df-0f688e74b85c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2098228765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.2098228765 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/1.kmac_burst_write.1077663727
Short name	T808
Test name
Test status
Simulation time	10921721369 ps
CPU time	328.32 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:42:37 PM PDT 24
Peak memory	228004 kb
Host	smart-f52535e4-5759-406c-afb1-60af0af025e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077663727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1077663727 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_burst_write/latest

Test location	/workspace/coverage/default/1.kmac_edn_timeout_error.1358793130
Short name	T1079
Test name
Test status
Simulation time	2003383543 ps
CPU time	41.08 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 12:37:57 PM PDT 24
Peak memory	223748 kb
Host	smart-c85e666b-fd11-49e3-9825-f99e9a7a1e53
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1358793130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.1358793130 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_mode_error.3771625644
Short name	T385
Test name
Test status
Simulation time	871317768 ps
CPU time	17.19 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 12:37:41 PM PDT 24
Peak memory	219940 kb
Host	smart-3a757b60-75cb-41d8-9459-fd3e03a9ff42
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3771625644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.3771625644 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_ready_error.1162620399
Short name	T877
Test name
Test status
Simulation time	2982194866 ps
CPU time	24.74 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:37:46 PM PDT 24
Peak memory	224044 kb
Host	smart-b2f11a74-52d4-4d12-8e15-74124212d90a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1162620399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.1162620399 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/1.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/1.kmac_entropy_refresh.2111793809
Short name	T426
Test name
Test status
Simulation time	170047490829 ps
CPU time	278.89 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:41:34 PM PDT 24
Peak memory	238956 kb
Host	smart-4e7482fc-9679-4564-b2e4-6f324627b5f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2111793809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.2111793809 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/1.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/1.kmac_error.1308203303
Short name	T763
Test name
Test status
Simulation time	8866916408 ps
CPU time	228.36 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:41:06 PM PDT 24
Peak memory	251056 kb
Host	smart-04fb562e-5c90-4b22-85e1-32c0eb38e987
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1308203303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.1308203303 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_error/latest

Test location	/workspace/coverage/default/1.kmac_key_error.4278650305
Short name	T992
Test name
Test status
Simulation time	1694507072 ps
CPU time	4.9 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:37:27 PM PDT 24
Peak memory	207300 kb
Host	smart-671af8f5-0d92-4691-a808-2452711658eb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4278650305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.4278650305 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_key_error/latest

Test location	/workspace/coverage/default/1.kmac_lc_escalation.2781353988
Short name	T40
Test name
Test status
Simulation time	151213232 ps
CPU time	1.35 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:37:13 PM PDT 24
Peak memory	215652 kb
Host	smart-9c917c1e-20e7-426c-bcf5-5574365da102
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2781353988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2781353988 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/1.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/1.kmac_long_msg_and_output.2549338234
Short name	T166
Test name
Test status
Simulation time	92163763102 ps
CPU time	1368.49 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 01:00:11 PM PDT 24
Peak memory	349484 kb
Host	smart-71c58d31-46c0-4c26-adf0-32209dd14da4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549338234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an d_output.2549338234 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/1.kmac_mubi.594056154
Short name	T1003
Test name
Test status
Simulation time	37256892145 ps
CPU time	305.91 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 12:42:22 PM PDT 24
Peak memory	249888 kb
Host	smart-02417397-5df1-410a-9eef-90b798183705
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=594056154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.594056154 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_mubi/latest

Test location	/workspace/coverage/default/1.kmac_sideload.1275502953
Short name	T685
Test name
Test status
Simulation time	13400697469 ps
CPU time	200.24 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:40:13 PM PDT 24
Peak memory	236220 kb
Host	smart-c2fd8eab-393d-486b-81b6-5b87791312b9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275502953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1275502953 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_sideload/latest

Test location	/workspace/coverage/default/1.kmac_smoke.1275740681
Short name	T830
Test name
Test status
Simulation time	5235738587 ps
CPU time	25.7 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:37:21 PM PDT 24
Peak memory	219624 kb
Host	smart-46b68e54-a6bb-44fc-8514-30d45f0c740f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1275740681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.1275740681 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_smoke/latest

Test location	/workspace/coverage/default/1.kmac_stress_all.2145854429
Short name	T123
Test name
Test status
Simulation time	232674921806 ps
CPU time	1576.77 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 01:03:35 PM PDT 24
Peak memory	373624 kb
Host	smart-4ce71118-32d0-4369-8bac-e0283b16a5f9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2145854429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2145854429 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all/latest

Test location	/workspace/coverage/default/1.kmac_stress_all_with_rand_reset.2238377012
Short name	T103
Test name
Test status
Simulation time	191497518535 ps
CPU time	1174.77 seconds
Started	Jun 13 12:37:03 PM PDT 24
Finished	Jun 13 12:56:39 PM PDT 24
Peak memory	349660 kb
Host	smart-061dd714-e068-4416-8d0e-edd83b04bd9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2238377012 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.2238377012 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac.31625912
Short name	T560
Test name
Test status
Simulation time	489136450 ps
CPU time	5.05 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:37:01 PM PDT 24
Peak memory	215768 kb
Host	smart-f65874eb-c361-46c9-90f8-7b88ee454a74
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31625912 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.kmac_test_vectors_kmac.31625912 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_kmac_xof.2678846921
Short name	T686
Test name
Test status
Simulation time	669302033 ps
CPU time	4.49 seconds
Started	Jun 13 12:37:06 PM PDT 24
Finished	Jun 13 12:37:12 PM PDT 24
Peak memory	209356 kb
Host	smart-10543868-d283-4d81-8719-2cbf22b3e324
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678846921 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.2678846921 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_224.3477044106
Short name	T645
Test name
Test status
Simulation time	337662639824 ps
CPU time	1836.29 seconds
Started	Jun 13 12:37:02 PM PDT 24
Finished	Jun 13 01:07:40 PM PDT 24
Peak memory	392360 kb
Host	smart-4969eacd-1296-4660-a938-520e36a838b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3477044106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3477044106 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_256.2271919404
Short name	T768
Test name
Test status
Simulation time	1154074170774 ps
CPU time	1800.07 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 01:07:19 PM PDT 24
Peak memory	387652 kb
Host	smart-eec2fef3-69da-41b4-881c-6f32c625aa44
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2271919404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.2271919404 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_384.4249456632
Short name	T822
Test name
Test status
Simulation time	908573966076 ps
CPU time	1664.31 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 01:04:55 PM PDT 24
Peak memory	344612 kb
Host	smart-6dc0af7f-8f67-477d-8918-af2bdf6a037e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4249456632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.4249456632 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_sha3_512.4135269937
Short name	T260
Test name
Test status
Simulation time	52261652709 ps
CPU time	948.84 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:53:06 PM PDT 24
Peak memory	298636 kb
Host	smart-777f9bf7-cf7b-477e-a438-5d3566981867
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4135269937 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.4135269937 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_128.2187668280
Short name	T660
Test name
Test status
Simulation time	520921868056 ps
CPU time	5105.43 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 02:02:28 PM PDT 24
Peak memory	665996 kb
Host	smart-40867f60-b9ba-4605-a479-d5eb0b5c8216
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2187668280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.2187668280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/1.kmac_test_vectors_shake_256.1494097052
Short name	T780
Test name
Test status
Simulation time	45731864266 ps
CPU time	3239.29 seconds
Started	Jun 13 12:37:01 PM PDT 24
Finished	Jun 13 01:31:02 PM PDT 24
Peak memory	575552 kb
Host	smart-0fe87bd3-585b-4cc5-a033-478d8c18192c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1494097052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.1494097052 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/1.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/10.kmac_app.2527361246
Short name	T657
Test name
Test status
Simulation time	12777345755 ps
CPU time	73.38 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:39:01 PM PDT 24
Peak memory	228084 kb
Host	smart-4fe28778-0ea9-45b7-9dc3-f8498e1ad8fc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527361246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.2527361246 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_app/latest

Test location	/workspace/coverage/default/10.kmac_burst_write.1885673059
Short name	T734
Test name
Test status
Simulation time	107006244639 ps
CPU time	626.34 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:48:10 PM PDT 24
Peak memory	231708 kb
Host	smart-0f6f443d-76e4-4f1d-b6be-372616192560
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1885673059 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.1885673059 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_burst_write/latest

Test location	/workspace/coverage/default/10.kmac_edn_timeout_error.3323226743
Short name	T424
Test name
Test status
Simulation time	405385659 ps
CPU time	7.06 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:37:30 PM PDT 24
Peak memory	223756 kb
Host	smart-be3e1f67-622e-4724-a7a4-fd8ce6034866
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3323226743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.3323226743 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_mode_error.3812421925
Short name	T921
Test name
Test status
Simulation time	1711888860 ps
CPU time	31.29 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:38:15 PM PDT 24
Peak memory	223832 kb
Host	smart-2429401b-24f7-41a7-9397-75f689fd1165
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3812421925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.3812421925 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/10.kmac_entropy_refresh.1403456113
Short name	T902
Test name
Test status
Simulation time	31447653709 ps
CPU time	136.81 seconds
Started	Jun 13 12:37:27 PM PDT 24
Finished	Jun 13 12:39:45 PM PDT 24
Peak memory	232780 kb
Host	smart-e2fa8228-f600-4bb6-89fa-024877e5156b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403456113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.1403456113 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/10.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/10.kmac_error.4010344829
Short name	T76
Test name
Test status
Simulation time	21905844250 ps
CPU time	131.11 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 12:39:37 PM PDT 24
Peak memory	240344 kb
Host	smart-f7cbbfa2-36f7-48e2-aab6-75f67c7cfa3a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4010344829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.4010344829 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_error/latest

Test location	/workspace/coverage/default/10.kmac_key_error.2010794793
Short name	T428
Test name
Test status
Simulation time	2339392863 ps
CPU time	6.02 seconds
Started	Jun 13 12:37:23 PM PDT 24
Finished	Jun 13 12:37:31 PM PDT 24
Peak memory	215736 kb
Host	smart-e2ac07e9-9b96-4dd6-89f0-2e156d9e09ec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010794793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.2010794793 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_key_error/latest

Test location	/workspace/coverage/default/10.kmac_lc_escalation.1156302432
Short name	T8
Test name
Test status
Simulation time	3464182000 ps
CPU time	44.81 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:38:26 PM PDT 24
Peak memory	232624 kb
Host	smart-631b7c18-a552-4af9-b61d-6b837fedd19a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1156302432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.1156302432 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/10.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/10.kmac_long_msg_and_output.986791835
Short name	T63
Test name
Test status
Simulation time	1955818328 ps
CPU time	41.4 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	224024 kb
Host	smart-4eb89671-c236-4b1b-93f4-47a7bc9f9725
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986791835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an d_output.986791835 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/10.kmac_sideload.641287601
Short name	T873
Test name
Test status
Simulation time	26952421049 ps
CPU time	85.25 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:39:00 PM PDT 24
Peak memory	226896 kb
Host	smart-8d7d394d-a017-4ddb-be8e-90a4dbdf5ea1
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641287601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.641287601 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_sideload/latest

Test location	/workspace/coverage/default/10.kmac_smoke.1274377265
Short name	T259
Test name
Test status
Simulation time	5251354629 ps
CPU time	41.98 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	216904 kb
Host	smart-0dffc75e-dc34-4deb-8407-4f133773ee31
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1274377265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.1274377265 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_smoke/latest

Test location	/workspace/coverage/default/10.kmac_stress_all.1320525280
Short name	T1002
Test name
Test status
Simulation time	70730980689 ps
CPU time	1400.99 seconds
Started	Jun 13 12:37:35 PM PDT 24
Finished	Jun 13 01:00:57 PM PDT 24
Peak memory	412480 kb
Host	smart-4716d96f-f307-4abc-a932-b5a1d14d82da
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1320525280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.1320525280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_stress_all/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac.372293174
Short name	T565
Test name
Test status
Simulation time	250271751 ps
CPU time	4.72 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:37:25 PM PDT 24
Peak memory	208812 kb
Host	smart-b257b0e7-5e31-4866-9131-4e71a807ac0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372293174 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 10.kmac_test_vectors_kmac.372293174 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3025661797
Short name	T477
Test name
Test status
Simulation time	126550149 ps
CPU time	3.65 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	215836 kb
Host	smart-888cf22a-598b-4802-a7a0-d64d13d018cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025661797 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3025661797 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_224.76237696
Short name	T858
Test name
Test status
Simulation time	375962248094 ps
CPU time	1807.26 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 01:07:54 PM PDT 24
Peak memory	377524 kb
Host	smart-75032da3-6362-4d62-8e6e-a4faa4056b8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=76237696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.76237696 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_256.2194104722
Short name	T910
Test name
Test status
Simulation time	76692605329 ps
CPU time	1410.54 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 01:00:47 PM PDT 24
Peak memory	371956 kb
Host	smart-6b45ec2f-d0fe-47ef-90a2-237efe2ee9ea
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2194104722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.2194104722 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_384.1493032709
Short name	T304
Test name
Test status
Simulation time	144206018991 ps
CPU time	1432.38 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 01:01:27 PM PDT 24
Peak memory	342720 kb
Host	smart-0df840a0-bd38-4da0-9d20-55738b6003a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1493032709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.1493032709 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_sha3_512.995269669
Short name	T1040
Test name
Test status
Simulation time	33971463168 ps
CPU time	928.24 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:53:17 PM PDT 24
Peak memory	300880 kb
Host	smart-c0615cf6-38ff-47e0-a9c9-c6eb1fd751e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=995269669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.995269669 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_128.2329319843
Short name	T1017
Test name
Test status
Simulation time	457932805162 ps
CPU time	4779.76 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 01:57:10 PM PDT 24
Peak memory	657688 kb
Host	smart-f0a34c39-691d-4955-8430-e965a28e4b0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2329319843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2329319843 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/10.kmac_test_vectors_shake_256.2992923734
Short name	T927
Test name
Test status
Simulation time	225023700045 ps
CPU time	4412.49 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 01:50:48 PM PDT 24
Peak memory	558716 kb
Host	smart-258b6a07-17ff-4c0f-bed7-2b288221f35d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2992923734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.2992923734 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/10.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/11.kmac_alert_test.2135292768
Short name	T868
Test name
Test status
Simulation time	134808321 ps
CPU time	0.8 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 12:37:25 PM PDT 24
Peak memory	205232 kb
Host	smart-4aabc797-6fd3-4424-a9f5-00f23de4b5bd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135292768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.2135292768 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_alert_test/latest

Test location	/workspace/coverage/default/11.kmac_app.2110326039
Short name	T585
Test name
Test status
Simulation time	18745162765 ps
CPU time	111.02 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:39:34 PM PDT 24
Peak memory	230772 kb
Host	smart-b061821c-9497-49a6-bd36-0b2dd2b1370b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110326039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.2110326039 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_app/latest

Test location	/workspace/coverage/default/11.kmac_burst_write.624382808
Short name	T1057
Test name
Test status
Simulation time	6376225713 ps
CPU time	523.39 seconds
Started	Jun 13 12:37:23 PM PDT 24
Finished	Jun 13 12:46:08 PM PDT 24
Peak memory	230200 kb
Host	smart-6a10475a-95b7-45e7-a686-61cce7a69927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=624382808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.624382808 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_burst_write/latest

Test location	/workspace/coverage/default/11.kmac_edn_timeout_error.1328747065
Short name	T715
Test name
Test status
Simulation time	5188649568 ps
CPU time	31.26 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	220392 kb
Host	smart-52ee6be2-59f7-49b2-b2ff-f31fd55ea146
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1328747065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.1328747065 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_mode_error.2926374239
Short name	T429
Test name
Test status
Simulation time	1183540096 ps
CPU time	28.47 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	223740 kb
Host	smart-f2406717-2876-4095-9a2d-bb16ff877b5e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2926374239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.2926374239 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/11.kmac_entropy_refresh.1145718900
Short name	T1025
Test name
Test status
Simulation time	11178268631 ps
CPU time	70.43 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:38:49 PM PDT 24
Peak memory	227772 kb
Host	smart-71c009fe-2734-4c23-971a-fa270ada50d5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1145718900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.1145718900 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/11.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/11.kmac_error.2371525820
Short name	T409
Test name
Test status
Simulation time	19649297048 ps
CPU time	366.13 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:43:46 PM PDT 24
Peak memory	256792 kb
Host	smart-4c0d70b0-25ed-46fd-a410-4a0616c87391
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371525820 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.2371525820 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_error/latest

Test location	/workspace/coverage/default/11.kmac_key_error.1604475663
Short name	T317
Test name
Test status
Simulation time	2491792387 ps
CPU time	4.37 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 12:37:31 PM PDT 24
Peak memory	215652 kb
Host	smart-c7c68958-330a-4dbd-9275-295ff48f6714
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604475663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.1604475663 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_key_error/latest

Test location	/workspace/coverage/default/11.kmac_lc_escalation.3264653982
Short name	T54
Test name
Test status
Simulation time	38572852 ps
CPU time	1.08 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:45 PM PDT 24
Peak memory	215644 kb
Host	smart-1f6e8690-4ffb-4ca2-8d60-75d48f90f1cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3264653982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.3264653982 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/11.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/11.kmac_long_msg_and_output.565941868
Short name	T909
Test name
Test status
Simulation time	19743587879 ps
CPU time	576.62 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:46:57 PM PDT 24
Peak memory	272800 kb
Host	smart-70a5c59f-7176-475b-b3c1-f45b77015257
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565941868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_an d_output.565941868 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/11.kmac_sideload.1863900080
Short name	T856
Test name
Test status
Simulation time	7828720648 ps
CPU time	164.2 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:40:24 PM PDT 24
Peak memory	232756 kb
Host	smart-e628cb7f-e155-4766-95cf-79f2512635a8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863900080 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1863900080 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_sideload/latest

Test location	/workspace/coverage/default/11.kmac_smoke.1927676693
Short name	T270
Test name
Test status
Simulation time	1094674681 ps
CPU time	4.81 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:37:20 PM PDT 24
Peak memory	221624 kb
Host	smart-fb9aa2c7-994e-46f6-a1c9-2d9bc7901af5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1927676693 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.1927676693 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_smoke/latest

Test location	/workspace/coverage/default/11.kmac_stress_all.2773767278
Short name	T277
Test name
Test status
Simulation time	117135787534 ps
CPU time	823.99 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:51:24 PM PDT 24
Peak memory	322968 kb
Host	smart-8ac196eb-87d8-47fd-a5bd-a265e129d873
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2773767278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.2773767278 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_stress_all/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac.2894768541
Short name	T785
Test name
Test status
Simulation time	74218697 ps
CPU time	3.93 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:37:51 PM PDT 24
Peak memory	215664 kb
Host	smart-fd3a1375-25de-4267-bae1-b6a9778b6f28
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894768541 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 11.kmac_test_vectors_kmac.2894768541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_kmac_xof.2645033025
Short name	T300
Test name
Test status
Simulation time	73126702 ps
CPU time	4.07 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:37:51 PM PDT 24
Peak memory	214948 kb
Host	smart-5d771ef7-1b90-46c9-916f-d2dbb2b5b014
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645033025 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_kmac_xof.2645033025 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_256.2853057337
Short name	T345
Test name
Test status
Simulation time	17552629227 ps
CPU time	1447.05 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 01:01:44 PM PDT 24
Peak memory	370300 kb
Host	smart-5c1aa134-0cce-4113-947c-55c0036e8a65
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2853057337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.2853057337 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_384.415985824
Short name	T811
Test name
Test status
Simulation time	46388472562 ps
CPU time	1262.4 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:58:40 PM PDT 24
Peak memory	331440 kb
Host	smart-de251473-b9b8-458a-a06f-e5a2dd5471a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=415985824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.415985824 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_sha3_512.3679722353
Short name	T318
Test name
Test status
Simulation time	378418969731 ps
CPU time	1015.03 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:54:34 PM PDT 24
Peak memory	296572 kb
Host	smart-ed4c20ac-f76e-4b51-8c42-5f4b2b2a3ce9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3679722353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.3679722353 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_128.3827995367
Short name	T556
Test name
Test status
Simulation time	222965720462 ps
CPU time	4518.47 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 01:53:07 PM PDT 24
Peak memory	652460 kb
Host	smart-458242c4-ff55-4a63-8967-bedeb1e0789e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3827995367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.3827995367 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/11.kmac_test_vectors_shake_256.27456123
Short name	T461
Test name
Test status
Simulation time	44480980246 ps
CPU time	3148 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 01:30:08 PM PDT 24
Peak memory	541188 kb
Host	smart-4e63ab43-afec-4022-83d3-f707af295698
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=27456123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.27456123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/11.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/12.kmac_alert_test.290089122
Short name	T542
Test name
Test status
Simulation time	52354198 ps
CPU time	0.77 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:37:47 PM PDT 24
Peak memory	205208 kb
Host	smart-7ac92c47-87d2-400d-b882-5b8ffcb3325b
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290089122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.290089122 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_alert_test/latest

Test location	/workspace/coverage/default/12.kmac_app.843802314
Short name	T532
Test name
Test status
Simulation time	10727882447 ps
CPU time	255.56 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:41:50 PM PDT 24
Peak memory	241380 kb
Host	smart-20943d6c-8c32-4e55-be56-4002cfe9f7cd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843802314 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.843802314 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_app/latest

Test location	/workspace/coverage/default/12.kmac_burst_write.1637292249
Short name	T281
Test name
Test status
Simulation time	101387210756 ps
CPU time	866.14 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 12:51:51 PM PDT 24
Peak memory	240404 kb
Host	smart-b414b085-33b3-4742-b77c-5a6f244002b9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637292249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1637292249 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_burst_write/latest

Test location	/workspace/coverage/default/12.kmac_edn_timeout_error.2223609707
Short name	T1053
Test name
Test status
Simulation time	4158321940 ps
CPU time	22.76 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:38:09 PM PDT 24
Peak memory	223704 kb
Host	smart-9d584b69-2168-4c72-9785-fb53e0793363
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2223609707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.2223609707 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_mode_error.849371798
Short name	T958
Test name
Test status
Simulation time	1719780450 ps
CPU time	22.28 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:38:01 PM PDT 24
Peak memory	218228 kb
Host	smart-527c3396-a388-471f-9542-967322f551d9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=849371798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.849371798 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/12.kmac_entropy_refresh.3204398858
Short name	T521
Test name
Test status
Simulation time	2177964314 ps
CPU time	15.07 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 12:37:47 PM PDT 24
Peak memory	217360 kb
Host	smart-45b552a4-c9f5-4dda-b1b3-bc9199e7580a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204398858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.3204398858 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/12.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/12.kmac_error.1068474722
Short name	T519
Test name
Test status
Simulation time	19314766070 ps
CPU time	397.06 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:44:11 PM PDT 24
Peak memory	262464 kb
Host	smart-c6900fa2-41be-41ee-b118-b62b87d3a08d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1068474722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.1068474722 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_error/latest

Test location	/workspace/coverage/default/12.kmac_key_error.12603543
Short name	T841
Test name
Test status
Simulation time	2651260861 ps
CPU time	3.14 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 12:37:30 PM PDT 24
Peak memory	215652 kb
Host	smart-ebb2dd73-f34d-453f-b0ce-e92bdd7c8e8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=12603543 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.12603543 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_key_error/latest

Test location	/workspace/coverage/default/12.kmac_lc_escalation.2828419854
Short name	T1080
Test name
Test status
Simulation time	346611140 ps
CPU time	1.33 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 12:37:27 PM PDT 24
Peak memory	217272 kb
Host	smart-021528a0-9945-40a7-966d-fa0400facbaa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2828419854 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2828419854 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/12.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/12.kmac_long_msg_and_output.2808384285
Short name	T188
Test name
Test status
Simulation time	54816012999 ps
CPU time	1197.73 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:57:42 PM PDT 24
Peak memory	320224 kb
Host	smart-62733641-187b-4667-a98b-c3fee07c1fa2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808384285 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_a nd_output.2808384285 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/12.kmac_sideload.2405558871
Short name	T162
Test name
Test status
Simulation time	31405725034 ps
CPU time	268.87 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:42:08 PM PDT 24
Peak memory	245288 kb
Host	smart-21a36525-da4d-4f9b-8802-1cab157419ab
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405558871 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.2405558871 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_sideload/latest

Test location	/workspace/coverage/default/12.kmac_smoke.3170752402
Short name	T487
Test name
Test status
Simulation time	3738200440 ps
CPU time	42.5 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	219292 kb
Host	smart-a80aba13-61f9-4300-b8a0-07759863c282
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3170752402 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.3170752402 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_smoke/latest

Test location	/workspace/coverage/default/12.kmac_stress_all.765982324
Short name	T25
Test name
Test status
Simulation time	37180867713 ps
CPU time	505.73 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:45:49 PM PDT 24
Peak memory	306316 kb
Host	smart-e857eb1e-30c9-46df-a2df-8a2db1da191a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=765982324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.765982324 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_stress_all/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac.1672216144
Short name	T793
Test name
Test status
Simulation time	124042134 ps
CPU time	4.25 seconds
Started	Jun 13 12:37:27 PM PDT 24
Finished	Jun 13 12:37:32 PM PDT 24
Peak memory	215832 kb
Host	smart-68c63efc-6923-4748-9da8-1beef7f6a6c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672216144 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 12.kmac_test_vectors_kmac.1672216144 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1976898009
Short name	T65
Test name
Test status
Simulation time	358550695 ps
CPU time	4.97 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:37:36 PM PDT 24
Peak memory	215816 kb
Host	smart-aa2170b3-13c3-4f69-b621-462c20b35134
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976898009 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1976898009 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_224.1475725308
Short name	T389
Test name
Test status
Simulation time	48799211093 ps
CPU time	1334.46 seconds
Started	Jun 13 12:37:27 PM PDT 24
Finished	Jun 13 12:59:42 PM PDT 24
Peak memory	369596 kb
Host	smart-daee3d6b-ab02-4c37-9f2a-ae3c050d851f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1475725308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1475725308 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_256.3208700039
Short name	T782
Test name
Test status
Simulation time	514291364058 ps
CPU time	1694.88 seconds
Started	Jun 13 12:37:31 PM PDT 24
Finished	Jun 13 01:05:47 PM PDT 24
Peak memory	377764 kb
Host	smart-608f190b-0062-492c-93f3-2b5384a4aeab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3208700039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.3208700039 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_384.96283148
Short name	T541
Test name
Test status
Simulation time	46070934178 ps
CPU time	1260.54 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:58:31 PM PDT 24
Peak memory	329260 kb
Host	smart-71901ac1-0b6d-409b-b9e4-5c3c716bf138
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=96283148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.96283148 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_sha3_512.3540902474
Short name	T182
Test name
Test status
Simulation time	74332933898 ps
CPU time	841.2 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:51:23 PM PDT 24
Peak memory	297632 kb
Host	smart-91e55c5d-b465-4a7e-b63a-ac66b276f075
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3540902474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.3540902474 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_128.835707060
Short name	T776
Test name
Test status
Simulation time	70928769190 ps
CPU time	4015.37 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 01:44:34 PM PDT 24
Peak memory	639132 kb
Host	smart-7d95cdb9-1756-43a8-9dc5-9c24847fdabe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=835707060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.835707060 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/12.kmac_test_vectors_shake_256.1496610932
Short name	T853
Test name
Test status
Simulation time	183835874201 ps
CPU time	3809.72 seconds
Started	Jun 13 12:37:48 PM PDT 24
Finished	Jun 13 01:41:19 PM PDT 24
Peak memory	542476 kb
Host	smart-fdf8fa68-e7bd-45b0-90fb-4ad3f9d7b760
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1496610932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1496610932 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/12.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/13.kmac_alert_test.3911732348
Short name	T962
Test name
Test status
Simulation time	46938183 ps
CPU time	0.75 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:37:45 PM PDT 24
Peak memory	205212 kb
Host	smart-9dce8fd8-7f53-448e-b32e-a64f9351fd32
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911732348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.3911732348 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_alert_test/latest

Test location	/workspace/coverage/default/13.kmac_app.2538055209
Short name	T1090
Test name
Test status
Simulation time	7088432282 ps
CPU time	133.59 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:39:55 PM PDT 24
Peak memory	233660 kb
Host	smart-29c37c74-b407-4520-a2db-2a2df4e1a745
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2538055209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2538055209 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_app/latest

Test location	/workspace/coverage/default/13.kmac_burst_write.1883254884
Short name	T44
Test name
Test status
Simulation time	7589375798 ps
CPU time	638.88 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:48:16 PM PDT 24
Peak memory	232692 kb
Host	smart-1b34018b-cd66-44a9-a75e-93ab24b2a80a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1883254884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.1883254884 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_burst_write/latest

Test location	/workspace/coverage/default/13.kmac_edn_timeout_error.4189588282
Short name	T421
Test name
Test status
Simulation time	193042697 ps
CPU time	6.96 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:37:42 PM PDT 24
Peak memory	215432 kb
Host	smart-e94e487b-4d99-4c0d-a632-28b893ea24de
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4189588282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.4189588282 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_mode_error.2904640029
Short name	T954
Test name
Test status
Simulation time	142362410 ps
CPU time	5.04 seconds
Started	Jun 13 12:37:54 PM PDT 24
Finished	Jun 13 12:38:00 PM PDT 24
Peak memory	218416 kb
Host	smart-07d22424-d71d-4dcd-a152-a1e758af21f0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2904640029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.2904640029 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/13.kmac_entropy_refresh.1310596207
Short name	T514
Test name
Test status
Simulation time	38042448108 ps
CPU time	176.64 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:40:36 PM PDT 24
Peak memory	238428 kb
Host	smart-b85d68f6-3f1b-4376-a7da-65dea5b3a1a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1310596207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.1310596207 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/13.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/13.kmac_error.3097947977
Short name	T310
Test name
Test status
Simulation time	36916274745 ps
CPU time	255.53 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:41:38 PM PDT 24
Peak memory	251476 kb
Host	smart-031dae63-0ae4-4414-92ea-bbaf5afb6888
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3097947977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.3097947977 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_error/latest

Test location	/workspace/coverage/default/13.kmac_key_error.2127083999
Short name	T60
Test name
Test status
Simulation time	176725453 ps
CPU time	1.13 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:37:42 PM PDT 24
Peak memory	205996 kb
Host	smart-b8f58f44-fba1-487b-a6cf-db6578bf3cf7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127083999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2127083999 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_key_error/latest

Test location	/workspace/coverage/default/13.kmac_lc_escalation.3669708359
Short name	T77
Test name
Test status
Simulation time	173825622 ps
CPU time	1.42 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:37:35 PM PDT 24
Peak memory	220236 kb
Host	smart-6716f6ab-bcb9-4332-b0ea-4256515a6826
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669708359 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.3669708359 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/13.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/13.kmac_long_msg_and_output.696259713
Short name	T1062
Test name
Test status
Simulation time	37321323898 ps
CPU time	1514.19 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 01:03:07 PM PDT 24
Peak memory	401528 kb
Host	smart-973144a3-5a2a-4546-86da-d3434d5b566a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696259713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an d_output.696259713 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/13.kmac_sideload.272236181
Short name	T994
Test name
Test status
Simulation time	10918539115 ps
CPU time	152.69 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:40:13 PM PDT 24
Peak memory	233196 kb
Host	smart-ea208a4f-1be6-4793-aecd-2025669b2df9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272236181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.272236181 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_sideload/latest

Test location	/workspace/coverage/default/13.kmac_smoke.1938859258
Short name	T960
Test name
Test status
Simulation time	625422124 ps
CPU time	10.03 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:53 PM PDT 24
Peak memory	221708 kb
Host	smart-146afcf6-6a48-4f55-a2c1-528f0061f946
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1938859258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.1938859258 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_smoke/latest

Test location	/workspace/coverage/default/13.kmac_stress_all.2353518109
Short name	T552
Test name
Test status
Simulation time	6409218890 ps
CPU time	145.35 seconds
Started	Jun 13 12:37:35 PM PDT 24
Finished	Jun 13 12:40:01 PM PDT 24
Peak memory	245728 kb
Host	smart-37489b60-568c-4788-9dcd-65efbc8c6676
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2353518109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.2353518109 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all/latest

Test location	/workspace/coverage/default/13.kmac_stress_all_with_rand_reset.1809909966
Short name	T105
Test name
Test status
Simulation time	188059900670 ps
CPU time	2661.25 seconds
Started	Jun 13 12:37:31 PM PDT 24
Finished	Jun 13 01:21:53 PM PDT 24
Peak memory	412772 kb
Host	smart-08a6206f-3471-41b1-bab1-2e472b088707
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1809909966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all_with_rand_reset.1809909966 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac.371675362
Short name	T729
Test name
Test status
Simulation time	239215171 ps
CPU time	4.18 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	208928 kb
Host	smart-f7cda578-18e0-4a97-9b84-26b0c6210dc3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371675362 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 13.kmac_test_vectors_kmac.371675362 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_kmac_xof.3309178892
Short name	T679
Test name
Test status
Simulation time	306744319 ps
CPU time	4 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:37:43 PM PDT 24
Peak memory	215800 kb
Host	smart-b4f9571d-13fa-48ae-873a-87ecf6cc402e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309178892 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_kmac_xof.3309178892 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_224.2740966876
Short name	T242
Test name
Test status
Simulation time	19916934353 ps
CPU time	1599.37 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 01:04:21 PM PDT 24
Peak memory	398000 kb
Host	smart-f5034131-0a70-4916-8471-f8bedfcb7e83
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2740966876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.2740966876 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_256.2781633054
Short name	T324
Test name
Test status
Simulation time	71267759005 ps
CPU time	1373.02 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 01:00:32 PM PDT 24
Peak memory	375848 kb
Host	smart-ecb02d52-6278-4d4a-96da-da6f772d135f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2781633054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.2781633054 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_384.912935349
Short name	T603
Test name
Test status
Simulation time	14275824917 ps
CPU time	1163.53 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:57:00 PM PDT 24
Peak memory	341952 kb
Host	smart-c2fc8b11-92b4-47c3-ba3c-50ef13d36290
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=912935349 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.912935349 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_sha3_512.3343467192
Short name	T512
Test name
Test status
Simulation time	119174548777 ps
CPU time	799.88 seconds
Started	Jun 13 12:37:28 PM PDT 24
Finished	Jun 13 12:50:49 PM PDT 24
Peak memory	296004 kb
Host	smart-1735cacf-6483-4555-a738-fa87acdb1f52
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3343467192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.3343467192 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_128.177325722
Short name	T292
Test name
Test status
Simulation time	424383725535 ps
CPU time	3906.9 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 01:42:44 PM PDT 24
Peak memory	652568 kb
Host	smart-85f33d57-94b9-40e3-b4f1-12d9b841140b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=177325722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.177325722 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/13.kmac_test_vectors_shake_256.169658018
Short name	T599
Test name
Test status
Simulation time	173310979230 ps
CPU time	3375.78 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 01:33:50 PM PDT 24
Peak memory	564636 kb
Host	smart-10e33d61-ee98-4871-b134-d3256a836762
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=169658018 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.169658018 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/13.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/14.kmac_alert_test.4079853239
Short name	T659
Test name
Test status
Simulation time	17571646 ps
CPU time	0.73 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:37:39 PM PDT 24
Peak memory	205212 kb
Host	smart-3a3f94f1-e8de-47bf-951c-fb1ddc292c56
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079853239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.4079853239 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_alert_test/latest

Test location	/workspace/coverage/default/14.kmac_app.1147160317
Short name	T617
Test name
Test status
Simulation time	7586298041 ps
CPU time	166.73 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:40:18 PM PDT 24
Peak memory	238136 kb
Host	smart-fbc0bef7-56ca-4177-a756-1730ac956ab9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1147160317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.1147160317 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_app/latest

Test location	/workspace/coverage/default/14.kmac_burst_write.1456457097
Short name	T922
Test name
Test status
Simulation time	21815427693 ps
CPU time	123.2 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:39:49 PM PDT 24
Peak memory	222376 kb
Host	smart-804f7394-a249-4fc4-a399-177832bde4dc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456457097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.1456457097 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_burst_write/latest

Test location	/workspace/coverage/default/14.kmac_edn_timeout_error.4057567041
Short name	T299
Test name
Test status
Simulation time	1057114408 ps
CPU time	16.82 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:37:50 PM PDT 24
Peak memory	223748 kb
Host	smart-8cfad991-54f5-47f3-b854-94d97baa16e6
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4057567041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.4057567041 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_mode_error.2631186963
Short name	T926
Test name
Test status
Simulation time	2710761130 ps
CPU time	27.56 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:37:58 PM PDT 24
Peak memory	223732 kb
Host	smart-ad0c4180-5fd1-4eda-b26b-52d283a28a63
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2631186963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.2631186963 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/14.kmac_entropy_refresh.2031230062
Short name	T893
Test name
Test status
Simulation time	9977155855 ps
CPU time	283.63 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:42:20 PM PDT 24
Peak memory	246448 kb
Host	smart-53c7aca1-863d-41fa-ab35-0d2594cb2f52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031230062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.2031230062 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/14.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/14.kmac_error.16094004
Short name	T499
Test name
Test status
Simulation time	55244379299 ps
CPU time	291.95 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:42:39 PM PDT 24
Peak memory	253388 kb
Host	smart-1d43e49c-cfa4-4b86-9871-9efdddad2ba8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16094004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.16094004 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_error/latest

Test location	/workspace/coverage/default/14.kmac_key_error.1657137687
Short name	T526
Test name
Test status
Simulation time	1280011315 ps
CPU time	6.77 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:37:46 PM PDT 24
Peak memory	215692 kb
Host	smart-56e2b636-60a6-4c1c-a975-5fe24ea76e9e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1657137687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.1657137687 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_key_error/latest

Test location	/workspace/coverage/default/14.kmac_lc_escalation.3133465969
Short name	T400
Test name
Test status
Simulation time	46965984 ps
CPU time	1.34 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:37:53 PM PDT 24
Peak memory	216780 kb
Host	smart-57573f35-6a66-4437-b98f-eb1f7cc9cf1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3133465969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3133465969 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/14.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/14.kmac_long_msg_and_output.3980605228
Short name	T1026
Test name
Test status
Simulation time	50081656748 ps
CPU time	452.87 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:45:20 PM PDT 24
Peak memory	266296 kb
Host	smart-46c3fb49-57a5-4fe5-b919-b97c7e1602a2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980605228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a nd_output.3980605228 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/14.kmac_sideload.918079817
Short name	T547
Test name
Test status
Simulation time	17734554083 ps
CPU time	344.29 seconds
Started	Jun 13 12:37:50 PM PDT 24
Finished	Jun 13 12:43:35 PM PDT 24
Peak memory	246720 kb
Host	smart-91c6644c-5a9b-4ffb-80a8-55ee9f7ca9d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918079817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.918079817 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_sideload/latest

Test location	/workspace/coverage/default/14.kmac_smoke.953646307
Short name	T957
Test name
Test status
Simulation time	2531211303 ps
CPU time	55.11 seconds
Started	Jun 13 12:37:48 PM PDT 24
Finished	Jun 13 12:38:44 PM PDT 24
Peak memory	217568 kb
Host	smart-77bae29d-3c9d-45b2-9db8-1070efa12ca2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=953646307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.953646307 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_smoke/latest

Test location	/workspace/coverage/default/14.kmac_stress_all.3768617145
Short name	T533
Test name
Test status
Simulation time	25878658065 ps
CPU time	1017.26 seconds
Started	Jun 13 12:37:50 PM PDT 24
Finished	Jun 13 12:54:48 PM PDT 24
Peak memory	346272 kb
Host	smart-a7d2604f-8911-48df-afdc-242041330667
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3768617145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all.3768617145 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all/latest

Test location	/workspace/coverage/default/14.kmac_stress_all_with_rand_reset.3963936645
Short name	T46
Test name
Test status
Simulation time	239137641447 ps
CPU time	1919.58 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 01:09:43 PM PDT 24
Peak memory	404712 kb
Host	smart-85568697-920d-42cb-b6fe-8efd9fbdc967
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3963936645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.3963936645 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac.789022853
Short name	T619
Test name
Test status
Simulation time	178844261 ps
CPU time	4.5 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:49 PM PDT 24
Peak memory	215812 kb
Host	smart-aaaef021-e3b7-4268-adb3-3104e846d7c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789022853 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 14.kmac_test_vectors_kmac.789022853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_kmac_xof.2889515982
Short name	T800
Test name
Test status
Simulation time	673560324 ps
CPU time	3.93 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:37:51 PM PDT 24
Peak memory	215768 kb
Host	smart-b1099759-9129-4cee-a9aa-d5e8d14b24e3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889515982 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_kmac_xof.2889515982 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_224.205683247
Short name	T589
Test name
Test status
Simulation time	150404884907 ps
CPU time	1919.59 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 01:09:26 PM PDT 24
Peak memory	388892 kb
Host	smart-93cf7e65-260a-4f7c-9e8c-abb0c3306a32
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=205683247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.205683247 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_256.2643531198
Short name	T714
Test name
Test status
Simulation time	46676394645 ps
CPU time	1451.26 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 01:01:46 PM PDT 24
Peak memory	374240 kb
Host	smart-780b8e8b-ded3-40bd-8e6c-40cabf0778f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2643531198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.2643531198 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_384.617960219
Short name	T387
Test name
Test status
Simulation time	72263362107 ps
CPU time	1362.61 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 01:00:07 PM PDT 24
Peak memory	337688 kb
Host	smart-d57aa32e-9dc1-4faa-9b34-10559b00655c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=617960219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.617960219 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_sha3_512.281959843
Short name	T829
Test name
Test status
Simulation time	34802780007 ps
CPU time	938.17 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:53:26 PM PDT 24
Peak memory	297908 kb
Host	smart-4ce67a51-e914-4e5c-9b50-35e745bf2a40
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=281959843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.281959843 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_128.661321811
Short name	T1055
Test name
Test status
Simulation time	55447619610 ps
CPU time	4019.73 seconds
Started	Jun 13 12:37:49 PM PDT 24
Finished	Jun 13 01:44:50 PM PDT 24
Peak memory	641184 kb
Host	smart-1e03c75c-74cf-4027-90e8-8d6805ff4abc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=661321811 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.661321811 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/14.kmac_test_vectors_shake_256.3339665593
Short name	T870
Test name
Test status
Simulation time	299555201021 ps
CPU time	4041.88 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 01:44:57 PM PDT 24
Peak memory	568708 kb
Host	smart-2e5aa07c-d8ad-4526-bc14-4bdcaf698d9b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3339665593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3339665593 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/14.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/15.kmac_alert_test.3044490802
Short name	T945
Test name
Test status
Simulation time	17931798 ps
CPU time	0.76 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:37:41 PM PDT 24
Peak memory	205204 kb
Host	smart-fccf2740-cb36-48ca-b0bd-743aa3e9c2de
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044490802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3044490802 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_alert_test/latest

Test location	/workspace/coverage/default/15.kmac_app.2586767367
Short name	T903
Test name
Test status
Simulation time	17510782071 ps
CPU time	241.15 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:41:45 PM PDT 24
Peak memory	245500 kb
Host	smart-50525a54-83b4-496e-8f1c-833dec3bee82
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2586767367 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2586767367 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_app/latest

Test location	/workspace/coverage/default/15.kmac_burst_write.2189008988
Short name	T545
Test name
Test status
Simulation time	12209129774 ps
CPU time	98.03 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:39:25 PM PDT 24
Peak memory	221004 kb
Host	smart-62cfae55-f6c9-4537-8be7-3b4b90c7cf5f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2189008988 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.2189008988 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_burst_write/latest

Test location	/workspace/coverage/default/15.kmac_edn_timeout_error.2846454873
Short name	T207
Test name
Test status
Simulation time	294441849 ps
CPU time	22.66 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:37:59 PM PDT 24
Peak memory	218716 kb
Host	smart-011961f2-2504-4075-90b0-57936b2eec74
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2846454873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2846454873 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_mode_error.743353046
Short name	T1051
Test name
Test status
Simulation time	1752138458 ps
CPU time	31.15 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:38:25 PM PDT 24
Peak memory	220304 kb
Host	smart-d7c236d5-0c56-4576-8475-3d525d761350
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=743353046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.743353046 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/15.kmac_entropy_refresh.1186912364
Short name	T1082
Test name
Test status
Simulation time	13610353184 ps
CPU time	229.72 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:41:21 PM PDT 24
Peak memory	239748 kb
Host	smart-3c41efc7-468f-4b02-98ee-8768c0d3221a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186912364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1186912364 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/15.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/15.kmac_error.1566694860
Short name	T397
Test name
Test status
Simulation time	19442728233 ps
CPU time	84.32 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:39:18 PM PDT 24
Peak memory	240416 kb
Host	smart-9f9049c3-234c-4f6b-8739-adfe218c0049
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1566694860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1566694860 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_error/latest

Test location	/workspace/coverage/default/15.kmac_key_error.2519220690
Short name	T669
Test name
Test status
Simulation time	1361317363 ps
CPU time	7.07 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:37:42 PM PDT 24
Peak memory	215608 kb
Host	smart-2696fead-28e6-41cf-8349-a35f26f8fd9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519220690 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.2519220690 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_key_error/latest

Test location	/workspace/coverage/default/15.kmac_long_msg_and_output.3146897014
Short name	T653
Test name
Test status
Simulation time	129545037337 ps
CPU time	708.46 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:49:31 PM PDT 24
Peak memory	279392 kb
Host	smart-fb0f3c15-054f-4dc5-9d52-5015b41cc25f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146897014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a nd_output.3146897014 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/15.kmac_sideload.1351808161
Short name	T1042
Test name
Test status
Simulation time	31492299033 ps
CPU time	341.92 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:43:19 PM PDT 24
Peak memory	247272 kb
Host	smart-606531a6-9d2d-48f3-8c8e-af1ba94ac4d9
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351808161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1351808161 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_sideload/latest

Test location	/workspace/coverage/default/15.kmac_smoke.4060130818
Short name	T353
Test name
Test status
Simulation time	9328990411 ps
CPU time	55.79 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	216940 kb
Host	smart-f48568cf-ca9a-4422-b7d0-f6baa7742e16
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4060130818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.4060130818 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_smoke/latest

Test location	/workspace/coverage/default/15.kmac_stress_all.1699828842
Short name	T598
Test name
Test status
Simulation time	24638828803 ps
CPU time	461.69 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:45:30 PM PDT 24
Peak memory	283408 kb
Host	smart-7ed2801b-76f3-4bdf-8ec4-9db633597d55
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1699828842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1699828842 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all/latest

Test location	/workspace/coverage/default/15.kmac_stress_all_with_rand_reset.1047188954
Short name	T104
Test name
Test status
Simulation time	159763041371 ps
CPU time	2833.47 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 01:24:51 PM PDT 24
Peak memory	432480 kb
Host	smart-60c4f598-1a7f-47e8-8200-ed16ae1d0ce5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1047188954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all_with_rand_reset.1047188954 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac.1391558654
Short name	T395
Test name
Test status
Simulation time	251811991 ps
CPU time	3.88 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:37:38 PM PDT 24
Peak memory	215768 kb
Host	smart-3945b1d9-9379-4cdf-9c8a-6705e8fba20f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391558654 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 15.kmac_test_vectors_kmac.1391558654 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3215522541
Short name	T289
Test name
Test status
Simulation time	262046654 ps
CPU time	3.9 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:37:43 PM PDT 24
Peak memory	215764 kb
Host	smart-cc1e4fe5-98d9-46fe-a8da-0f9b5b6c4a01
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215522541 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3215522541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_224.1374441366
Short name	T828
Test name
Test status
Simulation time	64943994985 ps
CPU time	1752.56 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 01:06:51 PM PDT 24
Peak memory	392308 kb
Host	smart-b92e61c1-2cbb-4878-8560-1e0990a914bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1374441366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.1374441366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_256.261699967
Short name	T929
Test name
Test status
Simulation time	247182082088 ps
CPU time	1792.82 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 01:07:25 PM PDT 24
Peak memory	377312 kb
Host	smart-6af07060-5e01-4aaf-b466-894fa31cf157
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=261699967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.261699967 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_384.4130549717
Short name	T1008
Test name
Test status
Simulation time	14389427763 ps
CPU time	1016.08 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:54:31 PM PDT 24
Peak memory	332832 kb
Host	smart-8e990ffe-a032-4dd5-bd79-bba1431c13a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4130549717 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.4130549717 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_sha3_512.1365548416
Short name	T413
Test name
Test status
Simulation time	9531685400 ps
CPU time	793.48 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:50:54 PM PDT 24
Peak memory	292068 kb
Host	smart-567bcc51-460a-4e18-9728-e2da29b4f61d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1365548416 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.1365548416 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_128.1486884744
Short name	T350
Test name
Test status
Simulation time	101818367520 ps
CPU time	4148.72 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 01:46:50 PM PDT 24
Peak memory	652028 kb
Host	smart-13648331-0264-4a6b-a960-a053d0ea121d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1486884744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.1486884744 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/15.kmac_test_vectors_shake_256.3797849252
Short name	T243
Test name
Test status
Simulation time	98492934187 ps
CPU time	3600.91 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 01:37:47 PM PDT 24
Peak memory	563436 kb
Host	smart-98452ce3-d585-41f1-870b-bfefb5cb6965
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3797849252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.3797849252 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/15.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/16.kmac_alert_test.1838953631
Short name	T282
Test name
Test status
Simulation time	15358121 ps
CPU time	0.76 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:37:43 PM PDT 24
Peak memory	205232 kb
Host	smart-6a08a9de-62ea-4043-90aa-8016db8e6ecc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838953631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1838953631 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_alert_test/latest

Test location	/workspace/coverage/default/16.kmac_app.490051751
Short name	T1009
Test name
Test status
Simulation time	36927991718 ps
CPU time	181.25 seconds
Started	Jun 13 12:37:27 PM PDT 24
Finished	Jun 13 12:40:29 PM PDT 24
Peak memory	235132 kb
Host	smart-d5017744-d25c-4c91-9048-99d589c79d1d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490051751 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.490051751 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_app/latest

Test location	/workspace/coverage/default/16.kmac_burst_write.1465060044
Short name	T539
Test name
Test status
Simulation time	522653197 ps
CPU time	39.2 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:38:23 PM PDT 24
Peak memory	219360 kb
Host	smart-d35d38ae-c427-4f8b-a4fb-eca27f905a6f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1465060044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.1465060044 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_burst_write/latest

Test location	/workspace/coverage/default/16.kmac_edn_timeout_error.2070866872
Short name	T720
Test name
Test status
Simulation time	189946061 ps
CPU time	2.27 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:37:55 PM PDT 24
Peak memory	217696 kb
Host	smart-6df1d557-8940-4237-bb6b-499b307d3bdb
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2070866872 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.2070866872 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_mode_error.611979401
Short name	T648
Test name
Test status
Simulation time	640235395 ps
CPU time	5.74 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:37:53 PM PDT 24
Peak memory	223728 kb
Host	smart-683fbaf3-2cd6-467c-b798-779776a14f72
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=611979401 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.611979401 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/16.kmac_entropy_refresh.762715017
Short name	T913
Test name
Test status
Simulation time	43146260930 ps
CPU time	169.4 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:40:24 PM PDT 24
Peak memory	235796 kb
Host	smart-faf3c14f-91ea-4fad-851d-1c5f49ae8f70
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=762715017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.762715017 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/16.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/16.kmac_error.837364591
Short name	T618
Test name
Test status
Simulation time	1299218170 ps
CPU time	21.69 seconds
Started	Jun 13 12:37:50 PM PDT 24
Finished	Jun 13 12:38:12 PM PDT 24
Peak memory	236512 kb
Host	smart-8e5fdb37-fa5f-4ab3-b289-7f496560c979
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837364591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.837364591 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_error/latest

Test location	/workspace/coverage/default/16.kmac_key_error.1539103557
Short name	T719
Test name
Test status
Simulation time	4229368440 ps
CPU time	4.73 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:37:43 PM PDT 24
Peak memory	207512 kb
Host	smart-fe1f95cd-ec62-4536-93d9-42744c3a4cce
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1539103557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1539103557 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_key_error/latest

Test location	/workspace/coverage/default/16.kmac_lc_escalation.2581730227
Short name	T578
Test name
Test status
Simulation time	69429553 ps
CPU time	1.21 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:37:53 PM PDT 24
Peak memory	215620 kb
Host	smart-c71ab32c-9597-4579-9988-82285a09e13e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581730227 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2581730227 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/16.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/16.kmac_long_msg_and_output.2975629031
Short name	T739
Test name
Test status
Simulation time	152380202942 ps
CPU time	1097.49 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:56:03 PM PDT 24
Peak memory	317500 kb
Host	smart-0847264d-7b1d-4e90-a309-46b65384794b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975629031 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_a nd_output.2975629031 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/16.kmac_sideload.1897163246
Short name	T291
Test name
Test status
Simulation time	49368780523 ps
CPU time	299.47 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:42:39 PM PDT 24
Peak memory	246280 kb
Host	smart-950b098e-4506-40d7-9143-ab1449c708e6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897163246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1897163246 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_sideload/latest

Test location	/workspace/coverage/default/16.kmac_smoke.320831465
Short name	T377
Test name
Test status
Simulation time	1515178241 ps
CPU time	37.96 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:38:32 PM PDT 24
Peak memory	215880 kb
Host	smart-2c3f5b72-66a8-4e3e-9cd6-1f6606da5aeb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320831465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.320831465 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_smoke/latest

Test location	/workspace/coverage/default/16.kmac_stress_all.3991275105
Short name	T834
Test name
Test status
Simulation time	63226723271 ps
CPU time	443.32 seconds
Started	Jun 13 12:37:56 PM PDT 24
Finished	Jun 13 12:45:20 PM PDT 24
Peak memory	277432 kb
Host	smart-c032fd82-d374-477b-948c-0039d5691bae
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3991275105 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.3991275105 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_stress_all/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac.126256309
Short name	T806
Test name
Test status
Simulation time	655418429 ps
CPU time	4.59 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:37:52 PM PDT 24
Peak memory	215804 kb
Host	smart-e2da418f-9a91-435d-8efd-832185e224b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126256309 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 16.kmac_test_vectors_kmac.126256309 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_kmac_xof.571901277
Short name	T473
Test name
Test status
Simulation time	231679072 ps
CPU time	4.07 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	215812 kb
Host	smart-bb3c729a-a45d-4530-ae79-d1b0bce0fd45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571901277 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 16.kmac_test_vectors_kmac_xof.571901277 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_224.3525806377
Short name	T961
Test name
Test status
Simulation time	556488154970 ps
CPU time	1832.39 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 01:08:12 PM PDT 24
Peak memory	389008 kb
Host	smart-5e3f3932-ea6a-4f30-88c8-e138cb4aebe9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3525806377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.3525806377 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_384.1307834431
Short name	T731
Test name
Test status
Simulation time	55491227033 ps
CPU time	1128.89 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:56:34 PM PDT 24
Peak memory	340416 kb
Host	smart-fbba57d3-2666-42b1-84db-fdfa1a6362db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1307834431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1307834431 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_sha3_512.2739425536
Short name	T592
Test name
Test status
Simulation time	137426849750 ps
CPU time	806.55 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:51:07 PM PDT 24
Peak memory	297596 kb
Host	smart-3711d787-5f20-4335-9fc0-da170da314d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2739425536 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.2739425536 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_128.646734418
Short name	T975
Test name
Test status
Simulation time	321029841877 ps
CPU time	4151.32 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 01:46:54 PM PDT 24
Peak memory	661176 kb
Host	smart-b1d7d441-187d-4e9a-8371-210436d04060
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=646734418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.646734418 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/16.kmac_test_vectors_shake_256.389814139
Short name	T523
Test name
Test status
Simulation time	1028823809719 ps
CPU time	4376.87 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 01:50:30 PM PDT 24
Peak memory	558956 kb
Host	smart-cd330cf6-9e5b-495e-9cd5-0a770450a642
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=389814139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.389814139 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/16.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/17.kmac_alert_test.888799181
Short name	T976
Test name
Test status
Simulation time	13461973 ps
CPU time	0.78 seconds
Started	Jun 13 12:37:54 PM PDT 24
Finished	Jun 13 12:37:56 PM PDT 24
Peak memory	205240 kb
Host	smart-238dd929-3f68-4348-9c51-c36099f902e5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888799181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.888799181 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_alert_test/latest

Test location	/workspace/coverage/default/17.kmac_app.272148962
Short name	T850
Test name
Test status
Simulation time	926590120 ps
CPU time	4.5 seconds
Started	Jun 13 12:37:56 PM PDT 24
Finished	Jun 13 12:38:01 PM PDT 24
Peak memory	215820 kb
Host	smart-7ca5f4b3-49ea-4a69-ac16-f551f42b23b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=272148962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.272148962 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_app/latest

Test location	/workspace/coverage/default/17.kmac_burst_write.4132193562
Short name	T146
Test name
Test status
Simulation time	7344220951 ps
CPU time	346.37 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:43:29 PM PDT 24
Peak memory	228448 kb
Host	smart-203508e4-1337-44e7-9636-d5f183105885
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4132193562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.4132193562 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_burst_write/latest

Test location	/workspace/coverage/default/17.kmac_edn_timeout_error.2894382209
Short name	T390
Test name
Test status
Simulation time	282906020 ps
CPU time	19.42 seconds
Started	Jun 13 12:37:39 PM PDT 24
Finished	Jun 13 12:37:59 PM PDT 24
Peak memory	218384 kb
Host	smart-a9c77297-4b88-460e-a9bf-473b0a839850
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2894382209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.2894382209 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_mode_error.1650214242
Short name	T64
Test name
Test status
Simulation time	390211590 ps
CPU time	7.17 seconds
Started	Jun 13 12:38:06 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	215676 kb
Host	smart-d3cca94e-956a-4853-9a38-865f8a71eb19
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1650214242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1650214242 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/17.kmac_entropy_refresh.271186253
Short name	T249
Test name
Test status
Simulation time	81510909580 ps
CPU time	216.01 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:41:20 PM PDT 24
Peak memory	239000 kb
Host	smart-180f0408-f867-42fa-b83b-3b48e35492ba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=271186253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.271186253 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/17.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/17.kmac_error.1477613664
Short name	T408
Test name
Test status
Simulation time	4139854734 ps
CPU time	312.16 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:42:57 PM PDT 24
Peak memory	256752 kb
Host	smart-cfdf7490-ba62-4c1a-a5b4-ae1029ca05af
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1477613664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.1477613664 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_error/latest

Test location	/workspace/coverage/default/17.kmac_key_error.3473318320
Short name	T308
Test name
Test status
Simulation time	446217512 ps
CPU time	2.5 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 12:37:37 PM PDT 24
Peak memory	207424 kb
Host	smart-885b87ee-97f2-4813-9773-58a84cc93054
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3473318320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.3473318320 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_key_error/latest

Test location	/workspace/coverage/default/17.kmac_lc_escalation.752031695
Short name	T779
Test name
Test status
Simulation time	263560379 ps
CPU time	1.5 seconds
Started	Jun 13 12:37:54 PM PDT 24
Finished	Jun 13 12:37:56 PM PDT 24
Peak memory	215628 kb
Host	smart-d0d24664-16e8-480e-9dfc-51813f34f225
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=752031695 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.752031695 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/17.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/17.kmac_long_msg_and_output.4024731512
Short name	T837
Test name
Test status
Simulation time	41352834793 ps
CPU time	1664.12 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 01:05:40 PM PDT 24
Peak memory	423492 kb
Host	smart-b4006922-fdf3-4c85-a05d-d8dc4400ec06
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024731512 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a nd_output.4024731512 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/17.kmac_sideload.3526118232
Short name	T1029
Test name
Test status
Simulation time	11267513341 ps
CPU time	76.78 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 12:39:03 PM PDT 24
Peak memory	226696 kb
Host	smart-cf54df81-ae6c-49e5-8884-4a6fefb9288e
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526118232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.3526118232 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_sideload/latest

Test location	/workspace/coverage/default/17.kmac_smoke.2376834103
Short name	T638
Test name
Test status
Simulation time	720575168 ps
CPU time	28.55 seconds
Started	Jun 13 12:37:56 PM PDT 24
Finished	Jun 13 12:38:25 PM PDT 24
Peak memory	215776 kb
Host	smart-e98c99a0-39df-4441-ab17-88d8ecdf1377
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2376834103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.2376834103 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_smoke/latest

Test location	/workspace/coverage/default/17.kmac_stress_all.3485445199
Short name	T977
Test name
Test status
Simulation time	50657848665 ps
CPU time	1074.67 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:55:40 PM PDT 24
Peak memory	332836 kb
Host	smart-24818d98-7de8-425b-ae36-0980672e5d1f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3485445199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3485445199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_stress_all/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac.63393226
Short name	T108
Test name
Test status
Simulation time	366039462 ps
CPU time	4.05 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:37:50 PM PDT 24
Peak memory	215632 kb
Host	smart-585758e5-062a-4b9f-a9d9-e78e371548e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63393226 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 17.kmac_test_vectors_kmac.63393226 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_kmac_xof.922112394
Short name	T481
Test name
Test status
Simulation time	990024545 ps
CPU time	4.81 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 12:38:10 PM PDT 24
Peak memory	215656 kb
Host	smart-71537626-185d-45bf-8afa-7944f84c2875
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922112394 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 17.kmac_test_vectors_kmac_xof.922112394 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_224.2753306781
Short name	T256
Test name
Test status
Simulation time	396295032182 ps
CPU time	2098.52 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 01:12:45 PM PDT 24
Peak memory	399680 kb
Host	smart-a246fd5b-fd1f-4016-be8b-60a36b9b629f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2753306781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.2753306781 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_256.3588136377
Short name	T577
Test name
Test status
Simulation time	317936062253 ps
CPU time	1824.06 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 01:08:07 PM PDT 24
Peak memory	376480 kb
Host	smart-9b06645a-6cfa-4eb2-b1c0-5d80c005c689
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3588136377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.3588136377 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_384.4283883640
Short name	T498
Test name
Test status
Simulation time	772898547833 ps
CPU time	1396.62 seconds
Started	Jun 13 12:37:35 PM PDT 24
Finished	Jun 13 01:00:52 PM PDT 24
Peak memory	332400 kb
Host	smart-759da55a-de09-4609-8587-3149fd2cf406
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4283883640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.4283883640 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_sha3_512.1969309184
Short name	T1007
Test name
Test status
Simulation time	34537026168 ps
CPU time	965.97 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 12:54:02 PM PDT 24
Peak memory	298320 kb
Host	smart-9c6ba4bb-ddff-4163-9f00-2fa5e6c8c1ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1969309184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1969309184 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_128.3354340281
Short name	T163
Test name
Test status
Simulation time	176879891732 ps
CPU time	4812.05 seconds
Started	Jun 13 12:37:52 PM PDT 24
Finished	Jun 13 01:58:05 PM PDT 24
Peak memory	659396 kb
Host	smart-8531e2b6-d034-4e4f-b650-0002c4b47a27
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3354340281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.3354340281 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/17.kmac_test_vectors_shake_256.3872798279
Short name	T562
Test name
Test status
Simulation time	89565176117 ps
CPU time	3483.5 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 01:35:44 PM PDT 24
Peak memory	574876 kb
Host	smart-b6729011-26ad-4a79-9592-1170f51b37b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3872798279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3872798279 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/17.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/18.kmac_alert_test.1213196608
Short name	T956
Test name
Test status
Simulation time	53606424 ps
CPU time	0.82 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:37:39 PM PDT 24
Peak memory	205092 kb
Host	smart-4d5775ac-4ab7-4274-8438-dea344661656
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213196608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.1213196608 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_alert_test/latest

Test location	/workspace/coverage/default/18.kmac_app.1593197773
Short name	T441
Test name
Test status
Simulation time	74223977680 ps
CPU time	370.41 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 12:44:10 PM PDT 24
Peak memory	248792 kb
Host	smart-98b623c5-414d-4ae6-85db-513bd2a29f83
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593197773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1593197773 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_app/latest

Test location	/workspace/coverage/default/18.kmac_burst_write.3944012891
Short name	T1065
Test name
Test status
Simulation time	45793320360 ps
CPU time	725.43 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:49:49 PM PDT 24
Peak memory	230748 kb
Host	smart-c2ec13db-df82-4458-b524-3c2ad28b2752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944012891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3944012891 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_burst_write/latest

Test location	/workspace/coverage/default/18.kmac_edn_timeout_error.1487608623
Short name	T824
Test name
Test status
Simulation time	5025184976 ps
CPU time	23.26 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:38:08 PM PDT 24
Peak memory	219312 kb
Host	smart-ea06fdaa-a7df-42cf-926f-824d41656061
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1487608623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1487608623 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_mode_error.515370714
Short name	T891
Test name
Test status
Simulation time	3488377849 ps
CPU time	36 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:38:19 PM PDT 24
Peak memory	223872 kb
Host	smart-c4d5eab7-7df4-4614-a9cf-a3b4f88a3cd0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=515370714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.515370714 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/18.kmac_entropy_refresh.59469209
Short name	T643
Test name
Test status
Simulation time	9641331983 ps
CPU time	110.81 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:39:37 PM PDT 24
Peak memory	233752 kb
Host	smart-89b72486-8089-458b-b3b2-4ec1f67b4927
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=59469209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.59469209 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/18.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/18.kmac_error.3384157057
Short name	T946
Test name
Test status
Simulation time	3538150672 ps
CPU time	23.71 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:38:15 PM PDT 24
Peak memory	236300 kb
Host	smart-fd45ee83-0fbc-435d-bec5-659f96fd1424
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3384157057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.3384157057 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_error/latest

Test location	/workspace/coverage/default/18.kmac_long_msg_and_output.3598918747
Short name	T226
Test name
Test status
Simulation time	61730345899 ps
CPU time	1782.99 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 01:07:21 PM PDT 24
Peak memory	398484 kb
Host	smart-31c9421b-4841-49f4-9045-94b0dc60993b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598918747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a nd_output.3598918747 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/18.kmac_sideload.3819218580
Short name	T252
Test name
Test status
Simulation time	15964360191 ps
CPU time	323.01 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 12:43:11 PM PDT 24
Peak memory	244856 kb
Host	smart-b07c1d50-741d-487c-80e6-0f7e0ae962d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819218580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3819218580 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_sideload/latest

Test location	/workspace/coverage/default/18.kmac_smoke.891251360
Short name	T307
Test name
Test status
Simulation time	3393895275 ps
CPU time	12.46 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 12:38:08 PM PDT 24
Peak memory	217884 kb
Host	smart-03920c08-76a5-461f-a2cd-ceb428f3e725
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=891251360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.891251360 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_smoke/latest

Test location	/workspace/coverage/default/18.kmac_stress_all.3483392034
Short name	T414
Test name
Test status
Simulation time	31462530305 ps
CPU time	992.12 seconds
Started	Jun 13 12:38:00 PM PDT 24
Finished	Jun 13 12:54:33 PM PDT 24
Peak memory	364792 kb
Host	smart-7956257a-1054-490e-8b65-0fbc4ad1827d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3483392034 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.3483392034 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_stress_all/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac.2894896974
Short name	T459
Test name
Test status
Simulation time	869852069 ps
CPU time	4.7 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:37:56 PM PDT 24
Peak memory	215748 kb
Host	smart-a1f5ca39-c76c-4779-b498-b02043fd9562
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894896974 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 18.kmac_test_vectors_kmac.2894896974 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3707396716
Short name	T802
Test name
Test status
Simulation time	883505158 ps
CPU time	4.64 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 12:38:01 PM PDT 24
Peak memory	215720 kb
Host	smart-1c31f31f-fbbc-4fe1-81f8-304c91a5dcfc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707396716 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3707396716 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_224.3985216709
Short name	T454
Test name
Test status
Simulation time	193284881616 ps
CPU time	1865.44 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 01:09:00 PM PDT 24
Peak memory	375600 kb
Host	smart-ba24670d-0c50-4531-929e-100cccfcdff8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3985216709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.3985216709 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_256.2121459901
Short name	T537
Test name
Test status
Simulation time	17972580139 ps
CPU time	1475.15 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 01:02:18 PM PDT 24
Peak memory	372272 kb
Host	smart-cd2dff55-e9fd-42c5-b38e-e1a50529669a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2121459901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2121459901 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_384.513979342
Short name	T1006
Test name
Test status
Simulation time	69429024350 ps
CPU time	1351.02 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 01:00:27 PM PDT 24
Peak memory	339324 kb
Host	smart-a6c1e9e0-c2fd-4a7a-a060-622d197bda00
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=513979342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.513979342 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_sha3_512.1813648727
Short name	T174
Test name
Test status
Simulation time	98648308636 ps
CPU time	1015.37 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:54:40 PM PDT 24
Peak memory	293280 kb
Host	smart-8e9568a3-6755-4bb6-9e5c-9692b5828a8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1813648727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.1813648727 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_128.163692602
Short name	T266
Test name
Test status
Simulation time	229915288372 ps
CPU time	3984.13 seconds
Started	Jun 13 12:37:58 PM PDT 24
Finished	Jun 13 01:44:23 PM PDT 24
Peak memory	644980 kb
Host	smart-ff72253a-1cff-4e77-9291-820e75c21f7d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=163692602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.163692602 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/18.kmac_test_vectors_shake_256.3644729774
Short name	T766
Test name
Test status
Simulation time	792088035719 ps
CPU time	4140.45 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 01:46:49 PM PDT 24
Peak memory	551392 kb
Host	smart-a8a5b722-48c2-46e5-9de0-ba16e0e47792
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3644729774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.3644729774 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/18.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/19.kmac_alert_test.996738880
Short name	T509
Test name
Test status
Simulation time	16664261 ps
CPU time	0.81 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:44 PM PDT 24
Peak memory	205248 kb
Host	smart-f407b9fb-e42f-40c7-aac7-add0dcd11060
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996738880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.996738880 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_alert_test/latest

Test location	/workspace/coverage/default/19.kmac_app.2670512134
Short name	T579
Test name
Test status
Simulation time	12556670680 ps
CPU time	181.82 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:40:48 PM PDT 24
Peak memory	239992 kb
Host	smart-1f0334da-af10-4bdb-aa37-992ab97376e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670512134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2670512134 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_app/latest

Test location	/workspace/coverage/default/19.kmac_burst_write.1909566048
Short name	T561
Test name
Test status
Simulation time	142905942969 ps
CPU time	669.43 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:48:51 PM PDT 24
Peak memory	232416 kb
Host	smart-18a7f3d6-92a5-4943-b0be-82874dd9f0e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1909566048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.1909566048 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_burst_write/latest

Test location	/workspace/coverage/default/19.kmac_edn_timeout_error.3441552647
Short name	T1018
Test name
Test status
Simulation time	14233029835 ps
CPU time	41.89 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:38:28 PM PDT 24
Peak memory	223796 kb
Host	smart-05104216-63da-46e5-8e5c-79091924814e
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3441552647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.3441552647 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_mode_error.2976879742
Short name	T171
Test name
Test status
Simulation time	1804292194 ps
CPU time	11.9 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:37:57 PM PDT 24
Peak memory	222280 kb
Host	smart-40f0655c-3bcf-4b31-ad71-73b0053922c9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2976879742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.2976879742 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/19.kmac_entropy_refresh.3351577267
Short name	T531
Test name
Test status
Simulation time	530188700 ps
CPU time	5.45 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:37:57 PM PDT 24
Peak memory	223936 kb
Host	smart-1d158e0d-eb6e-450b-b8d7-e07dc9dee397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3351577267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.3351577267 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/19.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/19.kmac_error.2390319862
Short name	T817
Test name
Test status
Simulation time	15873144258 ps
CPU time	129.15 seconds
Started	Jun 13 12:37:57 PM PDT 24
Finished	Jun 13 12:40:07 PM PDT 24
Peak memory	248548 kb
Host	smart-fb266e0b-66d3-4809-aa4a-307f84e7094f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2390319862 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.2390319862 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_error/latest

Test location	/workspace/coverage/default/19.kmac_key_error.2525328439
Short name	T993
Test name
Test status
Simulation time	695865385 ps
CPU time	2.26 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 12:38:02 PM PDT 24
Peak memory	215716 kb
Host	smart-464f5d54-9cc1-4879-ad47-4781d5c5bde8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2525328439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.2525328439 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_key_error/latest

Test location	/workspace/coverage/default/19.kmac_long_msg_and_output.3901628656
Short name	T953
Test name
Test status
Simulation time	242664039298 ps
CPU time	1935.38 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 01:10:08 PM PDT 24
Peak memory	429084 kb
Host	smart-5869e227-fcc2-4212-8ac5-abdde5bb828b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901628656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a nd_output.3901628656 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/19.kmac_sideload.1777271962
Short name	T771
Test name
Test status
Simulation time	19084787891 ps
CPU time	363.41 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 12:44:03 PM PDT 24
Peak memory	247268 kb
Host	smart-43d9f5c4-51d3-4d5b-a6f9-af1422b54e3a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777271962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1777271962 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_sideload/latest

Test location	/workspace/coverage/default/19.kmac_smoke.3513309309
Short name	T641
Test name
Test status
Simulation time	1940982393 ps
CPU time	32.08 seconds
Started	Jun 13 12:38:03 PM PDT 24
Finished	Jun 13 12:38:36 PM PDT 24
Peak memory	219556 kb
Host	smart-2a00e58f-df21-489d-9986-8ac88aa29a7f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3513309309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.3513309309 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_smoke/latest

Test location	/workspace/coverage/default/19.kmac_stress_all.3199258578
Short name	T92
Test name
Test status
Simulation time	292448126024 ps
CPU time	1463.73 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 01:02:08 PM PDT 24
Peak memory	382408 kb
Host	smart-a53730d5-b338-4a3e-ad46-34d95ee82bdc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3199258578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.3199258578 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all/latest

Test location	/workspace/coverage/default/19.kmac_stress_all_with_rand_reset.2275676702
Short name	T442
Test name
Test status
Simulation time	62078657418 ps
CPU time	460.59 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:45:26 PM PDT 24
Peak memory	273032 kb
Host	smart-ef38b241-9905-4098-817b-b6ff8fdcb5ae
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2275676702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all_with_rand_reset.2275676702 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac.1026749526
Short name	T865
Test name
Test status
Simulation time	662561096 ps
CPU time	4.28 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:37:50 PM PDT 24
Peak memory	215816 kb
Host	smart-baeb1091-669c-4efe-939c-c8883b672a07
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026749526 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 19.kmac_test_vectors_kmac.1026749526 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_kmac_xof.954230349
Short name	T701
Test name
Test status
Simulation time	1199645337 ps
CPU time	4.85 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	215792 kb
Host	smart-1c2700b3-c6b7-4bde-9961-5521846f4729
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954230349 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 19.kmac_test_vectors_kmac_xof.954230349 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_224.3655349887
Short name	T177
Test name
Test status
Simulation time	50987967302 ps
CPU time	1427.99 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 01:01:42 PM PDT 24
Peak memory	375616 kb
Host	smart-06cbb0da-604b-44ab-8999-086d2d4b6a43
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3655349887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.3655349887 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_256.2967232300
Short name	T240
Test name
Test status
Simulation time	435685063470 ps
CPU time	1823.9 seconds
Started	Jun 13 12:37:45 PM PDT 24
Finished	Jun 13 01:08:11 PM PDT 24
Peak memory	372736 kb
Host	smart-f4f7ebb3-590c-4f8f-bcbf-65ca2321a698
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2967232300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.2967232300 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_384.119123554
Short name	T275
Test name
Test status
Simulation time	47141241078 ps
CPU time	1259.5 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:58:38 PM PDT 24
Peak memory	336352 kb
Host	smart-423d6929-7b7e-49ca-93da-2f37376feb52
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=119123554 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.119123554 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_sha3_512.4006514721
Short name	T161
Test name
Test status
Simulation time	136530329001 ps
CPU time	904.42 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:52:50 PM PDT 24
Peak memory	296052 kb
Host	smart-fed1f9c7-7aea-4a04-916e-595ec8e4d0da
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4006514721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.4006514721 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_128.3976386090
Short name	T743
Test name
Test status
Simulation time	269296963426 ps
CPU time	5095.89 seconds
Started	Jun 13 12:37:35 PM PDT 24
Finished	Jun 13 02:02:32 PM PDT 24
Peak memory	658080 kb
Host	smart-61bb7124-eec1-4d01-baff-f8b713bf8fbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3976386090 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.3976386090 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/19.kmac_test_vectors_shake_256.970050168
Short name	T1052
Test name
Test status
Simulation time	772616800456 ps
CPU time	3996.19 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 01:44:22 PM PDT 24
Peak memory	550460 kb
Host	smart-fb2c7ceb-958b-4cda-90b6-cd389d1c1cb7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=970050168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.970050168 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/19.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/2.kmac_alert_test.1584822039
Short name	T494
Test name
Test status
Simulation time	40267007 ps
CPU time	0.77 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 12:37:27 PM PDT 24
Peak memory	205228 kb
Host	smart-0502c7eb-edc6-40ec-be44-2911bc9c17fb
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584822039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.1584822039 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_alert_test/latest

Test location	/workspace/coverage/default/2.kmac_app_with_partial_data.114920743
Short name	T721
Test name
Test status
Simulation time	10334516633 ps
CPU time	37.55 seconds
Started	Jun 13 12:37:38 PM PDT 24
Finished	Jun 13 12:38:16 PM PDT 24
Peak memory	224140 kb
Host	smart-609700fe-4622-4910-9bde-01a9e1fdd166
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=114920743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.114920743 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/2.kmac_burst_write.3323173344
Short name	T791
Test name
Test status
Simulation time	3222702095 ps
CPU time	69.93 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 12:38:07 PM PDT 24
Peak memory	219920 kb
Host	smart-4a6a68a2-8262-41b5-95d2-a61894ed4cd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3323173344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3323173344 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_burst_write/latest

Test location	/workspace/coverage/default/2.kmac_edn_timeout_error.3185592667
Short name	T170
Test name
Test status
Simulation time	433952013 ps
CPU time	15.38 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 12:37:12 PM PDT 24
Peak memory	233624 kb
Host	smart-9f5a4bc8-094f-4162-aa80-815845829916
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3185592667 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.3185592667 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_mode_error.363816525
Short name	T703
Test name
Test status
Simulation time	1489925402 ps
CPU time	34.46 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	223724 kb
Host	smart-04645eaf-db8f-4559-93b6-aa39a34343fa
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=363816525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.363816525 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/2.kmac_entropy_refresh.1009041033
Short name	T320
Test name
Test status
Simulation time	30084573908 ps
CPU time	254.32 seconds
Started	Jun 13 12:36:50 PM PDT 24
Finished	Jun 13 12:41:08 PM PDT 24
Peak memory	243568 kb
Host	smart-b5fa3f87-17e4-4059-a742-e49364942018
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009041033 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1009041033 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/2.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/2.kmac_error.1603924777
Short name	T237
Test name
Test status
Simulation time	2936183119 ps
CPU time	49.9 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:38:11 PM PDT 24
Peak memory	233276 kb
Host	smart-e34e0fa7-5c1a-4f73-b4b1-2be95ca7a28e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1603924777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.1603924777 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_error/latest

Test location	/workspace/coverage/default/2.kmac_key_error.4226257530
Short name	T463
Test name
Test status
Simulation time	247807157 ps
CPU time	1.97 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:36:57 PM PDT 24
Peak memory	207460 kb
Host	smart-e31bced1-ec7c-4ded-af62-3616a1960d19
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4226257530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.4226257530 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_key_error/latest

Test location	/workspace/coverage/default/2.kmac_lc_escalation.2657236098
Short name	T55
Test name
Test status
Simulation time	140452436 ps
CPU time	1.29 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 12:36:58 PM PDT 24
Peak memory	215644 kb
Host	smart-ec31a00f-6b14-44d8-af18-10d780ef07f3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657236098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.2657236098 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/2.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/2.kmac_long_msg_and_output.2497827229
Short name	T787
Test name
Test status
Simulation time	11828699325 ps
CPU time	878.16 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:51:47 PM PDT 24
Peak memory	314368 kb
Host	smart-4227f869-9802-4ef7-a149-811e5927d271
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497827229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an d_output.2497827229 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/2.kmac_mubi.2328085980
Short name	T440
Test name
Test status
Simulation time	6495156987 ps
CPU time	84.36 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:38:20 PM PDT 24
Peak memory	229216 kb
Host	smart-2f11d76b-18fa-454d-bd97-497bfe2f75e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2328085980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.2328085980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_mubi/latest

Test location	/workspace/coverage/default/2.kmac_sec_cm.1115995408
Short name	T11
Test name
Test status
Simulation time	2886262562 ps
CPU time	35.27 seconds
Started	Jun 13 12:36:58 PM PDT 24
Finished	Jun 13 12:37:35 PM PDT 24
Peak memory	252840 kb
Host	smart-30fe5c7e-1702-47d3-9ea7-212066b34a6d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115995408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1115995408 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/2.kmac_sec_cm/latest

Test location	/workspace/coverage/default/2.kmac_sideload.1868151002
Short name	T399
Test name
Test status
Simulation time	5822754170 ps
CPU time	114.97 seconds
Started	Jun 13 12:37:26 PM PDT 24
Finished	Jun 13 12:39:22 PM PDT 24
Peak memory	232264 kb
Host	smart-adde7bf2-bac1-400e-b949-bbe7a1cbfffa
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868151002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.1868151002 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_sideload/latest

Test location	/workspace/coverage/default/2.kmac_smoke.860442415
Short name	T874
Test name
Test status
Simulation time	5416018349 ps
CPU time	29.75 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:37:43 PM PDT 24
Peak memory	219100 kb
Host	smart-b3183be8-017d-4f33-bb0e-99a3f0b85cac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860442415 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.860442415 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_smoke/latest

Test location	/workspace/coverage/default/2.kmac_stress_all.767699047
Short name	T1050
Test name
Test status
Simulation time	9815525431 ps
CPU time	449.03 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:44:44 PM PDT 24
Peak memory	287724 kb
Host	smart-44f3cdc5-bcc1-469c-9102-29c6f6c91bba
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=767699047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.767699047 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all/latest

Test location	/workspace/coverage/default/2.kmac_stress_all_with_rand_reset.1199922560
Short name	T842
Test name
Test status
Simulation time	7429185147 ps
CPU time	242.38 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:41:14 PM PDT 24
Peak memory	255252 kb
Host	smart-0f28e2de-81fa-4abb-92f6-781edb1f1b78
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1199922560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.1199922560 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac.163400814
Short name	T920
Test name
Test status
Simulation time	168743711 ps
CPU time	4.19 seconds
Started	Jun 13 12:36:50 PM PDT 24
Finished	Jun 13 12:36:58 PM PDT 24
Peak memory	215800 kb
Host	smart-9d308994-8c12-4fbe-906a-c39ac1024fc9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163400814 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.kmac_test_vectors_kmac.163400814 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_kmac_xof.3381710918
Short name	T1083
Test name
Test status
Simulation time	244211058 ps
CPU time	4.32 seconds
Started	Jun 13 12:37:28 PM PDT 24
Finished	Jun 13 12:37:34 PM PDT 24
Peak memory	215848 kb
Host	smart-3c618b67-8870-49e7-968e-fa167d52d389
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381710918 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.3381710918 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_224.4034505093
Short name	T15
Test name
Test status
Simulation time	132654127858 ps
CPU time	1769.51 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 01:06:45 PM PDT 24
Peak memory	377716 kb
Host	smart-71551674-8c8e-4287-8e30-c60667dd7035
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4034505093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.4034505093 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_256.3457158977
Short name	T941
Test name
Test status
Simulation time	188866223553 ps
CPU time	1820.97 seconds
Started	Jun 13 12:36:57 PM PDT 24
Finished	Jun 13 01:07:19 PM PDT 24
Peak memory	370648 kb
Host	smart-a43c86d8-5f3d-4112-aa23-b9fcb37dc468
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3457158977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3457158977 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_384.2595853612
Short name	T704
Test name
Test status
Simulation time	14095726612 ps
CPU time	1121.13 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:56:03 PM PDT 24
Peak memory	333072 kb
Host	smart-2fd95005-4b0e-4f81-9c00-8caa5af67798
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2595853612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.2595853612 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_sha3_512.421613350
Short name	T752
Test name
Test status
Simulation time	32792752599 ps
CPU time	903.05 seconds
Started	Jun 13 12:37:26 PM PDT 24
Finished	Jun 13 12:52:31 PM PDT 24
Peak memory	295920 kb
Host	smart-a825ea67-f75c-4252-bd0e-f4d3c8b73731
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=421613350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.421613350 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/2.kmac_test_vectors_shake_128.1167668640
Short name	T262
Test name
Test status
Simulation time	836611010393 ps
CPU time	4405.63 seconds
Started	Jun 13 12:36:54 PM PDT 24
Finished	Jun 13 01:50:23 PM PDT 24
Peak memory	639740 kb
Host	smart-3c80f06b-100c-4c9d-bf7e-93626b0da0a4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1167668640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.1167668640 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/2.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_alert_test.3469643128
Short name	T522
Test name
Test status
Simulation time	15909695 ps
CPU time	0.78 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	205232 kb
Host	smart-3fb94c49-fe4e-4e69-aeb8-62a991c0ebec
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469643128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.3469643128 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_alert_test/latest

Test location	/workspace/coverage/default/20.kmac_app.358960951
Short name	T113
Test name
Test status
Simulation time	1804573124 ps
CPU time	71.97 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:38:57 PM PDT 24
Peak memory	228624 kb
Host	smart-55220c89-c933-4bab-ae47-28dcf2ff92fa
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=358960951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.358960951 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_app/latest

Test location	/workspace/coverage/default/20.kmac_burst_write.4274225476
Short name	T615
Test name
Test status
Simulation time	11065437076 ps
CPU time	345.53 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:43:59 PM PDT 24
Peak memory	228516 kb
Host	smart-1cfa6acc-84eb-4457-bbf0-bdc07560e2be
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4274225476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.4274225476 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_burst_write/latest

Test location	/workspace/coverage/default/20.kmac_entropy_refresh.959775943
Short name	T217
Test name
Test status
Simulation time	1015279410 ps
CPU time	51.9 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:38:38 PM PDT 24
Peak memory	224204 kb
Host	smart-58da5723-b248-438c-88c8-580262fa75da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=959775943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.959775943 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/20.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/20.kmac_key_error.3188922451
Short name	T1010
Test name
Test status
Simulation time	2531577642 ps
CPU time	2.43 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 12:37:51 PM PDT 24
Peak memory	207576 kb
Host	smart-8eeea995-a659-40de-91cc-bc3d8bdd9e32
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188922451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3188922451 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_key_error/latest

Test location	/workspace/coverage/default/20.kmac_lc_escalation.1906459724
Short name	T35
Test name
Test status
Simulation time	961424086 ps
CPU time	8.4 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:37:51 PM PDT 24
Peak memory	224028 kb
Host	smart-46bd1ffe-8024-4896-84f4-72db150cd106
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1906459724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.1906459724 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/20.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/20.kmac_long_msg_and_output.2114846980
Short name	T214
Test name
Test status
Simulation time	11882226831 ps
CPU time	247.97 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:41:57 PM PDT 24
Peak memory	239612 kb
Host	smart-e6d27818-b892-4b8a-9392-933d7e4af054
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114846980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a nd_output.2114846980 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/20.kmac_sideload.1888351248
Short name	T1023
Test name
Test status
Simulation time	1065924097 ps
CPU time	81.63 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 12:39:22 PM PDT 24
Peak memory	225652 kb
Host	smart-2f80f023-d551-4208-a189-bf0574b476e7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888351248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.1888351248 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_sideload/latest

Test location	/workspace/coverage/default/20.kmac_smoke.425764914
Short name	T786
Test name
Test status
Simulation time	10325450916 ps
CPU time	28.6 seconds
Started	Jun 13 12:37:49 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	217348 kb
Host	smart-c13b07b3-fae2-42d0-9f8b-56f640057294
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=425764914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.425764914 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_smoke/latest

Test location	/workspace/coverage/default/20.kmac_stress_all.526104350
Short name	T1031
Test name
Test status
Simulation time	34668417162 ps
CPU time	936.43 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:53:17 PM PDT 24
Peak memory	315000 kb
Host	smart-77f30454-efec-4b8e-84fe-d15d746b32f8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=526104350 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.526104350 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_stress_all/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac.898197485
Short name	T1015
Test name
Test status
Simulation time	798296048 ps
CPU time	3.7 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:37:52 PM PDT 24
Peak memory	215772 kb
Host	smart-7f3a7f7a-dea2-42bd-bef7-a8456adcbc10
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898197485 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 20.kmac_test_vectors_kmac.898197485 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_kmac_xof.2270398537
Short name	T480
Test name
Test status
Simulation time	262430701 ps
CPU time	3.83 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 12:37:59 PM PDT 24
Peak memory	215796 kb
Host	smart-c6475ac0-18a4-4eb4-9064-2efff41544ce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270398537 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_kmac_xof.2270398537 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_224.3975160092
Short name	T813
Test name
Test status
Simulation time	19100109964 ps
CPU time	1513.02 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 01:02:59 PM PDT 24
Peak memory	396748 kb
Host	smart-a65ef942-ca3f-4702-8843-a0fbcc72af47
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3975160092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.3975160092 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_256.3688399521
Short name	T71
Test name
Test status
Simulation time	66771998362 ps
CPU time	1667.97 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 01:05:34 PM PDT 24
Peak memory	375904 kb
Host	smart-a8185f3a-0269-46dc-a00e-3e7b4fa62f6a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3688399521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3688399521 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_384.401066660
Short name	T183
Test name
Test status
Simulation time	47949831610 ps
CPU time	1306.13 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:59:32 PM PDT 24
Peak memory	335660 kb
Host	smart-e3ae5c27-260d-444c-b414-6b6a1c88f39a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=401066660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.401066660 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_sha3_512.4094769389
Short name	T991
Test name
Test status
Simulation time	38383692648 ps
CPU time	758.23 seconds
Started	Jun 13 12:38:00 PM PDT 24
Finished	Jun 13 12:50:39 PM PDT 24
Peak memory	296972 kb
Host	smart-f853cccb-9665-4b90-aac5-0c3a997fbab7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4094769389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.4094769389 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_128.215954950
Short name	T875
Test name
Test status
Simulation time	51498970770 ps
CPU time	3833 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 01:41:37 PM PDT 24
Peak memory	642500 kb
Host	smart-274504ef-bfa7-4fd1-a496-fe8141248741
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=215954950 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.215954950 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/20.kmac_test_vectors_shake_256.2040607056
Short name	T443
Test name
Test status
Simulation time	44320406600 ps
CPU time	3458.53 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 01:35:45 PM PDT 24
Peak memory	564220 kb
Host	smart-c2cb837e-4262-4873-935c-09da96fa0454
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2040607056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.2040607056 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/20.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/21.kmac_alert_test.1082886312
Short name	T912
Test name
Test status
Simulation time	52513250 ps
CPU time	0.75 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:37:46 PM PDT 24
Peak memory	205092 kb
Host	smart-ed8b6157-5f70-410e-8020-2bec846d5c98
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082886312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1082886312 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_alert_test/latest

Test location	/workspace/coverage/default/21.kmac_app.4100705256
Short name	T360
Test name
Test status
Simulation time	3290634386 ps
CPU time	40.56 seconds
Started	Jun 13 12:37:43 PM PDT 24
Finished	Jun 13 12:38:25 PM PDT 24
Peak memory	224220 kb
Host	smart-c305935d-81ca-43c5-88c7-bba8a894ce7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100705256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.4100705256 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_app/latest

Test location	/workspace/coverage/default/21.kmac_burst_write.3802586264
Short name	T805
Test name
Test status
Simulation time	71329384601 ps
CPU time	399.58 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:44:28 PM PDT 24
Peak memory	227924 kb
Host	smart-a511c4d4-c457-4a88-8138-01526c473864
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3802586264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3802586264 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_burst_write/latest

Test location	/workspace/coverage/default/21.kmac_error.1994963124
Short name	T518
Test name
Test status
Simulation time	46593591177 ps
CPU time	453.54 seconds
Started	Jun 13 12:37:48 PM PDT 24
Finished	Jun 13 12:45:23 PM PDT 24
Peak memory	265720 kb
Host	smart-0f620bbc-2f07-4884-bebe-426d03ed254a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1994963124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.1994963124 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_error/latest

Test location	/workspace/coverage/default/21.kmac_key_error.2925360548
Short name	T264
Test name
Test status
Simulation time	1164195752 ps
CPU time	6.05 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 12:38:15 PM PDT 24
Peak memory	215692 kb
Host	smart-e30d23a1-70b0-467c-b673-3821960b918c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2925360548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.2925360548 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_key_error/latest

Test location	/workspace/coverage/default/21.kmac_lc_escalation.430277795
Short name	T364
Test name
Test status
Simulation time	3187865788 ps
CPU time	14.46 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:38:17 PM PDT 24
Peak memory	224040 kb
Host	smart-1ce6ed2c-4002-4160-ba63-a0c318253ff1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=430277795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.430277795 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/21.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/21.kmac_long_msg_and_output.1709135525
Short name	T193
Test name
Test status
Simulation time	10108468926 ps
CPU time	239.38 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 12:42:04 PM PDT 24
Peak memory	240448 kb
Host	smart-a9a48e9e-905a-4484-803e-b204738f7e41
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709135525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a nd_output.1709135525 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/21.kmac_sideload.542718625
Short name	T979
Test name
Test status
Simulation time	13315204134 ps
CPU time	287.67 seconds
Started	Jun 13 12:37:56 PM PDT 24
Finished	Jun 13 12:42:44 PM PDT 24
Peak memory	242568 kb
Host	smart-f9250b1e-2208-4bb1-ab3c-0ef392b3212b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542718625 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.542718625 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_sideload/latest

Test location	/workspace/coverage/default/21.kmac_smoke.3577661371
Short name	T767
Test name
Test status
Simulation time	439172810 ps
CPU time	21.87 seconds
Started	Jun 13 12:37:42 PM PDT 24
Finished	Jun 13 12:38:06 PM PDT 24
Peak memory	221876 kb
Host	smart-6c67e349-1200-4f47-99e8-edaaf38417d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3577661371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.3577661371 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_smoke/latest

Test location	/workspace/coverage/default/21.kmac_stress_all.2692131515
Short name	T699
Test name
Test status
Simulation time	121950969288 ps
CPU time	946.35 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:53:35 PM PDT 24
Peak memory	344924 kb
Host	smart-ae8ddcf1-e643-46d3-8b91-abdb9b2ae851
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2692131515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.2692131515 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all/latest

Test location	/workspace/coverage/default/21.kmac_stress_all_with_rand_reset.436590218
Short name	T936
Test name
Test status
Simulation time	77681302433 ps
CPU time	1139.62 seconds
Started	Jun 13 12:37:51 PM PDT 24
Finished	Jun 13 12:56:51 PM PDT 24
Peak memory	348840 kb
Host	smart-96ef5728-d139-456e-950f-967770f245b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=436590218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.436590218 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac.3219933848
Short name	T1064
Test name
Test status
Simulation time	129373320 ps
CPU time	4.08 seconds
Started	Jun 13 12:38:01 PM PDT 24
Finished	Jun 13 12:38:06 PM PDT 24
Peak memory	215880 kb
Host	smart-b4a17e0f-55bb-4ac1-a4aa-346babb5131c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219933848 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 21.kmac_test_vectors_kmac.3219933848 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_kmac_xof.961077089
Short name	T889
Test name
Test status
Simulation time	94094235 ps
CPU time	3.85 seconds
Started	Jun 13 12:38:01 PM PDT 24
Finished	Jun 13 12:38:06 PM PDT 24
Peak memory	215764 kb
Host	smart-39832ef0-ca69-4bf1-a7e6-2e54fb473aa7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961077089 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 21.kmac_test_vectors_kmac_xof.961077089 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_224.2434335058
Short name	T405
Test name
Test status
Simulation time	19235748985 ps
CPU time	1469.77 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 01:02:41 PM PDT 24
Peak memory	377740 kb
Host	smart-2d28af4d-2323-4c83-aa60-e469e7c227b5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2434335058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.2434335058 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_256.3253105221
Short name	T613
Test name
Test status
Simulation time	37391775861 ps
CPU time	1473.06 seconds
Started	Jun 13 12:37:48 PM PDT 24
Finished	Jun 13 01:02:22 PM PDT 24
Peak memory	378336 kb
Host	smart-cd45146f-6d92-43f9-8a62-0c0e33ce56f6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3253105221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.3253105221 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_384.2803104660
Short name	T398
Test name
Test status
Simulation time	403823455421 ps
CPU time	1349.75 seconds
Started	Jun 13 12:37:58 PM PDT 24
Finished	Jun 13 01:00:28 PM PDT 24
Peak memory	329024 kb
Host	smart-9cb5fb9f-8ab5-45db-8b9f-427f4b0a186e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2803104660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.2803104660 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_sha3_512.3978494672
Short name	T616
Test name
Test status
Simulation time	39403888611 ps
CPU time	801.53 seconds
Started	Jun 13 12:37:58 PM PDT 24
Finished	Jun 13 12:51:20 PM PDT 24
Peak memory	294304 kb
Host	smart-5a9ebf23-73c1-4e16-9e39-aa92febd26b6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3978494672 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.3978494672 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/21.kmac_test_vectors_shake_256.3414960827
Short name	T770
Test name
Test status
Simulation time	3084131462548 ps
CPU time	4869.27 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 01:58:58 PM PDT 24
Peak memory	558712 kb
Host	smart-d6814e1a-e2cf-4c55-ad98-9ac41358da77
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3414960827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3414960827 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/21.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/22.kmac_alert_test.22019618
Short name	T316
Test name
Test status
Simulation time	59288667 ps
CPU time	0.8 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 12:38:11 PM PDT 24
Peak memory	205228 kb
Host	smart-e7227cc8-1bb9-48ed-80be-8f14f7b8e8e7
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22019618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.22019618 +enable_mas king=0 +sw_key_masked=0
Directory	/workspace/22.kmac_alert_test/latest

Test location	/workspace/coverage/default/22.kmac_app.744938958
Short name	T623
Test name
Test status
Simulation time	1532441765 ps
CPU time	56.27 seconds
Started	Jun 13 12:38:01 PM PDT 24
Finished	Jun 13 12:38:58 PM PDT 24
Peak memory	224824 kb
Host	smart-95680785-3f5a-4659-b97c-ed3b76418351
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=744938958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.744938958 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_app/latest

Test location	/workspace/coverage/default/22.kmac_burst_write.809492790
Short name	T527
Test name
Test status
Simulation time	1728385835 ps
CPU time	23.61 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 12:38:32 PM PDT 24
Peak memory	223992 kb
Host	smart-6bd04a78-ecb5-446e-9fbe-d709fe606279
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=809492790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.809492790 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_burst_write/latest

Test location	/workspace/coverage/default/22.kmac_entropy_refresh.3882595488
Short name	T491
Test name
Test status
Simulation time	25311895936 ps
CPU time	192.56 seconds
Started	Jun 13 12:37:46 PM PDT 24
Finished	Jun 13 12:41:01 PM PDT 24
Peak memory	238772 kb
Host	smart-5850477a-a39d-4672-af33-9cf565928289
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882595488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.3882595488 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/22.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/22.kmac_error.2040524280
Short name	T357
Test name
Test status
Simulation time	2197219588 ps
CPU time	157.5 seconds
Started	Jun 13 12:37:54 PM PDT 24
Finished	Jun 13 12:40:32 PM PDT 24
Peak memory	248528 kb
Host	smart-e75d5986-fcdb-4905-89dc-7141ad8550a3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040524280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.2040524280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_error/latest

Test location	/workspace/coverage/default/22.kmac_key_error.993879775
Short name	T626
Test name
Test status
Simulation time	1443868926 ps
CPU time	3.57 seconds
Started	Jun 13 12:37:55 PM PDT 24
Finished	Jun 13 12:38:00 PM PDT 24
Peak memory	207492 kb
Host	smart-c5447106-e3c9-4369-b4f3-4a914d69d525
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=993879775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.993879775 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_key_error/latest

Test location	/workspace/coverage/default/22.kmac_lc_escalation.1697527453
Short name	T691
Test name
Test status
Simulation time	104242675 ps
CPU time	1.2 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:37:55 PM PDT 24
Peak memory	215756 kb
Host	smart-f7f76858-5531-48fe-9ea5-2d66de2439a5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697527453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1697527453 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/22.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/22.kmac_long_msg_and_output.2495388200
Short name	T248
Test name
Test status
Simulation time	3714728148 ps
CPU time	90.79 seconds
Started	Jun 13 12:38:08 PM PDT 24
Finished	Jun 13 12:39:39 PM PDT 24
Peak memory	224024 kb
Host	smart-c22f769d-0595-429b-9048-ae3a2731bf82
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495388200 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a nd_output.2495388200 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/22.kmac_sideload.1134205113
Short name	T1005
Test name
Test status
Simulation time	47550188855 ps
CPU time	291.73 seconds
Started	Jun 13 12:37:47 PM PDT 24
Finished	Jun 13 12:42:40 PM PDT 24
Peak memory	247788 kb
Host	smart-52a973b5-6d5d-4f37-92c6-db903798b34a
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134205113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1134205113 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_sideload/latest

Test location	/workspace/coverage/default/22.kmac_smoke.3376056507
Short name	T160
Test name
Test status
Simulation time	31591924146 ps
CPU time	49.52 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 12:39:00 PM PDT 24
Peak memory	215884 kb
Host	smart-5e00a135-4f0d-462a-8e86-10dc28c0f36a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3376056507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.3376056507 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_smoke/latest

Test location	/workspace/coverage/default/22.kmac_stress_all.270217669
Short name	T968
Test name
Test status
Simulation time	52145599302 ps
CPU time	961.77 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:54:05 PM PDT 24
Peak memory	330828 kb
Host	smart-4fabf661-11d7-4953-a668-82d3f45a4d21
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=270217669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.270217669 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_stress_all/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac.4102857128
Short name	T231
Test name
Test status
Simulation time	70136819 ps
CPU time	4.15 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:38:07 PM PDT 24
Peak memory	215844 kb
Host	smart-4f103a20-33cc-4e1d-afb8-373561b285f9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102857128 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 22.kmac_test_vectors_kmac.4102857128 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1057333473
Short name	T220
Test name
Test status
Simulation time	242120180 ps
CPU time	3.86 seconds
Started	Jun 13 12:37:52 PM PDT 24
Finished	Jun 13 12:37:56 PM PDT 24
Peak memory	215840 kb
Host	smart-1d9c6e31-aa22-4c52-a773-b9adcf9e5e8b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057333473 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1057333473 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_224.4036949952
Short name	T255
Test name
Test status
Simulation time	86965151252 ps
CPU time	1668.64 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 01:05:53 PM PDT 24
Peak memory	398100 kb
Host	smart-57b7d49d-b9d6-4af5-8ce9-505db373527c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4036949952 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.4036949952 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_256.3782120741
Short name	T911
Test name
Test status
Simulation time	252891007342 ps
CPU time	1707.73 seconds
Started	Jun 13 12:37:52 PM PDT 24
Finished	Jun 13 01:06:20 PM PDT 24
Peak memory	371528 kb
Host	smart-49234404-1dba-4ea1-9c62-b6ea7fe2cbc2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3782120741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3782120741 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_384.1608718843
Short name	T111
Test name
Test status
Simulation time	93828204490 ps
CPU time	1196.38 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 12:58:06 PM PDT 24
Peak memory	334916 kb
Host	smart-d4b7dead-c5db-4822-af7e-99d7ba7ac7a2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1608718843 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.1608718843 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_sha3_512.1811068459
Short name	T863
Test name
Test status
Simulation time	43595917179 ps
CPU time	894.63 seconds
Started	Jun 13 12:37:57 PM PDT 24
Finished	Jun 13 12:52:52 PM PDT 24
Peak memory	293024 kb
Host	smart-86314b68-e9fa-4c71-ac0e-a9a10f1a2db6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1811068459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.1811068459 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_128.3527441189
Short name	T164
Test name
Test status
Simulation time	50847327031 ps
CPU time	3927.52 seconds
Started	Jun 13 12:38:01 PM PDT 24
Finished	Jun 13 01:43:30 PM PDT 24
Peak memory	650548 kb
Host	smart-848a81ac-6854-4f07-b568-7749c26aa2d9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3527441189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.3527441189 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/22.kmac_test_vectors_shake_256.3912039856
Short name	T346
Test name
Test status
Simulation time	218924072089 ps
CPU time	4193.84 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 01:47:54 PM PDT 24
Peak memory	570044 kb
Host	smart-446a46bc-6fbb-4c37-9b0e-af88174e0124
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3912039856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.3912039856 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/22.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/23.kmac_alert_test.394110833
Short name	T963
Test name
Test status
Simulation time	124582702 ps
CPU time	0.81 seconds
Started	Jun 13 12:38:03 PM PDT 24
Finished	Jun 13 12:38:05 PM PDT 24
Peak memory	205228 kb
Host	smart-08932d94-0213-49e3-95b5-dbe00ba9771c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394110833 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.394110833 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_alert_test/latest

Test location	/workspace/coverage/default/23.kmac_app.1788093490
Short name	T321
Test name
Test status
Simulation time	3929852490 ps
CPU time	87.85 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:39:31 PM PDT 24
Peak memory	228876 kb
Host	smart-dbec9232-e47a-4ea0-9b85-a6d9ef0c04cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788093490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1788093490 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_app/latest

Test location	/workspace/coverage/default/23.kmac_burst_write.2055335506
Short name	T1034
Test name
Test status
Simulation time	67859676347 ps
CPU time	251.34 seconds
Started	Jun 13 12:38:00 PM PDT 24
Finished	Jun 13 12:42:13 PM PDT 24
Peak memory	234520 kb
Host	smart-2d3ab977-aa0b-4119-8e8c-fc8f64a671d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2055335506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.2055335506 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_burst_write/latest

Test location	/workspace/coverage/default/23.kmac_entropy_refresh.1235116817
Short name	T988
Test name
Test status
Simulation time	16416751599 ps
CPU time	304.91 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 12:43:09 PM PDT 24
Peak memory	245300 kb
Host	smart-91327f58-ef03-4e50-9eda-e98a24c38f3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1235116817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.1235116817 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/23.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/23.kmac_error.689398804
Short name	T332
Test name
Test status
Simulation time	74849443182 ps
CPU time	279.76 seconds
Started	Jun 13 12:37:59 PM PDT 24
Finished	Jun 13 12:42:40 PM PDT 24
Peak memory	256760 kb
Host	smart-75ceb32a-f0bb-40bb-a797-6a32f3e17c71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=689398804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.689398804 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_error/latest

Test location	/workspace/coverage/default/23.kmac_key_error.2924855794
Short name	T482
Test name
Test status
Simulation time	1547430927 ps
CPU time	7.81 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	207476 kb
Host	smart-6f314504-850a-4d6e-9337-a7d69d5f03e6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2924855794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.2924855794 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_key_error/latest

Test location	/workspace/coverage/default/23.kmac_lc_escalation.2702777730
Short name	T449
Test name
Test status
Simulation time	43758695 ps
CPU time	1.38 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 12:38:07 PM PDT 24
Peak memory	215704 kb
Host	smart-981e8186-7b7d-4f3a-a157-5ccb50d0f452
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2702777730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.2702777730 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/23.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/23.kmac_long_msg_and_output.2652879400
Short name	T69
Test name
Test status
Simulation time	28377164930 ps
CPU time	2194.63 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 01:14:43 PM PDT 24
Peak memory	474532 kb
Host	smart-72bfbf98-4583-4077-9984-163baedea789
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652879400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_a nd_output.2652879400 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/23.kmac_sideload.1712137023
Short name	T241
Test name
Test status
Simulation time	52182519296 ps
CPU time	386.19 seconds
Started	Jun 13 12:37:54 PM PDT 24
Finished	Jun 13 12:44:21 PM PDT 24
Peak memory	250308 kb
Host	smart-33406342-b63f-4260-8aa0-616f4fb2c815
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712137023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.1712137023 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_sideload/latest

Test location	/workspace/coverage/default/23.kmac_smoke.1150969324
Short name	T1091
Test name
Test status
Simulation time	1161771364 ps
CPU time	30.04 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:38:24 PM PDT 24
Peak memory	215948 kb
Host	smart-e486f997-af04-4d23-a50f-37dbbed8d37d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150969324 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1150969324 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_smoke/latest

Test location	/workspace/coverage/default/23.kmac_stress_all.2383731189
Short name	T478
Test name
Test status
Simulation time	17736272523 ps
CPU time	231.54 seconds
Started	Jun 13 12:38:14 PM PDT 24
Finished	Jun 13 12:42:07 PM PDT 24
Peak memory	272788 kb
Host	smart-a80ddd72-8fac-42a1-99ad-c2197c31fb3d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2383731189 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.2383731189 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_stress_all/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac.4002773149
Short name	T642
Test name
Test status
Simulation time	65696889 ps
CPU time	4.2 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	215800 kb
Host	smart-56d02f3f-dc2c-4648-93d4-38f31ed4491b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002773149 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 23.kmac_test_vectors_kmac.4002773149 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_kmac_xof.2150688488
Short name	T483
Test name
Test status
Simulation time	66135093 ps
CPU time	3.88 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 12:38:12 PM PDT 24
Peak memory	215836 kb
Host	smart-a7242d29-425b-4bc3-8b63-794b97edee8c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150688488 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_kmac_xof.2150688488 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_224.2528162222
Short name	T747
Test name
Test status
Simulation time	74714702489 ps
CPU time	1592.04 seconds
Started	Jun 13 12:37:57 PM PDT 24
Finished	Jun 13 01:04:30 PM PDT 24
Peak memory	389028 kb
Host	smart-18be19d5-14f0-4327-8574-9af1096e035b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2528162222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.2528162222 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_256.1157502954
Short name	T750
Test name
Test status
Simulation time	371333336958 ps
CPU time	1848.91 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 01:08:54 PM PDT 24
Peak memory	387040 kb
Host	smart-d877f36f-471f-4b72-964f-0c0d78688600
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1157502954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.1157502954 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_384.717614449
Short name	T186
Test name
Test status
Simulation time	27282215817 ps
CPU time	1220.27 seconds
Started	Jun 13 12:38:03 PM PDT 24
Finished	Jun 13 12:58:24 PM PDT 24
Peak memory	335344 kb
Host	smart-0b7b781e-034f-42b8-bb8a-53ee37bd91f5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=717614449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.717614449 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_sha3_512.2893039873
Short name	T740
Test name
Test status
Simulation time	128964680066 ps
CPU time	869.69 seconds
Started	Jun 13 12:38:01 PM PDT 24
Finished	Jun 13 12:52:31 PM PDT 24
Peak memory	292084 kb
Host	smart-1024e170-ad4b-49f2-9cd1-96dbbb39e7bc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2893039873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.2893039873 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_128.1352629037
Short name	T311
Test name
Test status
Simulation time	52242274021 ps
CPU time	4097.5 seconds
Started	Jun 13 12:38:03 PM PDT 24
Finished	Jun 13 01:46:21 PM PDT 24
Peak memory	645012 kb
Host	smart-748fdb5c-467b-4814-b1be-5b74536d1a3c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1352629037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.1352629037 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/23.kmac_test_vectors_shake_256.3651574662
Short name	T546
Test name
Test status
Simulation time	169893509077 ps
CPU time	4079.75 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 01:46:10 PM PDT 24
Peak memory	556136 kb
Host	smart-ec0f21ee-ec49-4fad-977c-2c09bfa1736e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3651574662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.3651574662 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/23.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/24.kmac_alert_test.775150962
Short name	T636
Test name
Test status
Simulation time	14899933 ps
CPU time	0.75 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 12:38:08 PM PDT 24
Peak memory	205224 kb
Host	smart-04c11dec-6d5e-4114-8a2d-5488a362b8ca
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775150962 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.775150962 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_alert_test/latest

Test location	/workspace/coverage/default/24.kmac_app.1560045567
Short name	T279
Test name
Test status
Simulation time	1163775251 ps
CPU time	5.58 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 12:38:11 PM PDT 24
Peak memory	215844 kb
Host	smart-3b21c5a5-2244-439e-972f-e23fe21589e0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1560045567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.1560045567 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_app/latest

Test location	/workspace/coverage/default/24.kmac_burst_write.3087653193
Short name	T888
Test name
Test status
Simulation time	91194755073 ps
CPU time	800.41 seconds
Started	Jun 13 12:38:00 PM PDT 24
Finished	Jun 13 12:51:21 PM PDT 24
Peak memory	231376 kb
Host	smart-3a2b0ffc-9794-42a4-81a8-8485f7700871
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3087653193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.3087653193 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_burst_write/latest

Test location	/workspace/coverage/default/24.kmac_entropy_refresh.4261696765
Short name	T981
Test name
Test status
Simulation time	39702908045 ps
CPU time	160.53 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 12:40:48 PM PDT 24
Peak memory	234896 kb
Host	smart-e86fb3a5-cc23-4129-8936-e0a5d5e7d12c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4261696765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.4261696765 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/24.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/24.kmac_error.3020243838
Short name	T30
Test name
Test status
Simulation time	9300192708 ps
CPU time	302.18 seconds
Started	Jun 13 12:38:16 PM PDT 24
Finished	Jun 13 12:43:18 PM PDT 24
Peak memory	265004 kb
Host	smart-2ba0c932-b373-4e65-a6e7-b52f0841c106
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3020243838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.3020243838 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_error/latest

Test location	/workspace/coverage/default/24.kmac_key_error.3426016851
Short name	T57
Test name
Test status
Simulation time	1428065103 ps
CPU time	3.36 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:16 PM PDT 24
Peak memory	207488 kb
Host	smart-df8fd47c-7244-4624-a86d-b675521fa78c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3426016851 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.3426016851 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_key_error/latest

Test location	/workspace/coverage/default/24.kmac_lc_escalation.2878236514
Short name	T567
Test name
Test status
Simulation time	25936855 ps
CPU time	1.35 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 12:38:09 PM PDT 24
Peak memory	220548 kb
Host	smart-90b1fb18-8af4-474f-a09f-ba96540fa250
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878236514 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2878236514 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/24.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/24.kmac_long_msg_and_output.2440805129
Short name	T497
Test name
Test status
Simulation time	53313229572 ps
CPU time	1191.79 seconds
Started	Jun 13 12:38:00 PM PDT 24
Finished	Jun 13 12:57:53 PM PDT 24
Peak memory	337416 kb
Host	smart-709ffc3d-1d18-4131-a8df-e28f8306f8b8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440805129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_a nd_output.2440805129 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/24.kmac_sideload.4265750235
Short name	T884
Test name
Test status
Simulation time	11410659084 ps
CPU time	214.18 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:41:37 PM PDT 24
Peak memory	240304 kb
Host	smart-7b8987b3-0b39-4ace-8357-898778376e24
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265750235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.4265750235 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_sideload/latest

Test location	/workspace/coverage/default/24.kmac_smoke.3905839251
Short name	T392
Test name
Test status
Simulation time	138125640 ps
CPU time	7.09 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 12:38:13 PM PDT 24
Peak memory	218744 kb
Host	smart-7678c286-be83-4385-98e1-f50303433c2d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3905839251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3905839251 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_smoke/latest

Test location	/workspace/coverage/default/24.kmac_stress_all.3635407595
Short name	T799
Test name
Test status
Simulation time	179653411178 ps
CPU time	1495.21 seconds
Started	Jun 13 12:38:07 PM PDT 24
Finished	Jun 13 01:03:03 PM PDT 24
Peak memory	415284 kb
Host	smart-f07b06ed-fe79-48c1-800a-30a2ee310f87
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3635407595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3635407595 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all/latest

Test location	/workspace/coverage/default/24.kmac_stress_all_with_rand_reset.2877924253
Short name	T45
Test name
Test status
Simulation time	39289120779 ps
CPU time	399.29 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:44:52 PM PDT 24
Peak memory	288316 kb
Host	smart-8c26e85d-3bd5-457e-b12f-11e20c11b803
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2877924253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all_with_rand_reset.2877924253 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac.3400902594
Short name	T452
Test name
Test status
Simulation time	263066248 ps
CPU time	3.68 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	215712 kb
Host	smart-3b79e3db-6bb5-452e-b796-1adfdfd1ef30
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400902594 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 24.kmac_test_vectors_kmac.3400902594 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_kmac_xof.1008659899
Short name	T690
Test name
Test status
Simulation time	255737023 ps
CPU time	4.86 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 12:38:09 PM PDT 24
Peak memory	215792 kb
Host	smart-6ff189eb-c174-4a5b-b0d6-c39ea13750e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008659899 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_kmac_xof.1008659899 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_224.2781028890
Short name	T596
Test name
Test status
Simulation time	66517082185 ps
CPU time	1714.79 seconds
Started	Jun 13 12:38:03 PM PDT 24
Finished	Jun 13 01:06:38 PM PDT 24
Peak memory	386584 kb
Host	smart-973eed91-de05-4533-bcb3-6591dd3c45c3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2781028890 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2781028890 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_256.4168491626
Short name	T253
Test name
Test status
Simulation time	79622647036 ps
CPU time	1376.42 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 01:01:06 PM PDT 24
Peak memory	370284 kb
Host	smart-e5d3fba0-a1bf-4cf5-bb13-5fdc530870cb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4168491626 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_256.4168491626 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_384.2065312433
Short name	T1071
Test name
Test status
Simulation time	159880261036 ps
CPU time	1291.04 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 12:59:36 PM PDT 24
Peak memory	332100 kb
Host	smart-3bbda161-2119-4304-a763-db7c62165e67
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2065312433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.2065312433 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_sha3_512.3014507339
Short name	T999
Test name
Test status
Simulation time	33213052284 ps
CPU time	891.82 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:53:05 PM PDT 24
Peak memory	296652 kb
Host	smart-af6fb9d1-ea48-443c-b742-723f640c08db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3014507339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.3014507339 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_128.1224426885
Short name	T184
Test name
Test status
Simulation time	68606417072 ps
CPU time	3965.98 seconds
Started	Jun 13 12:38:11 PM PDT 24
Finished	Jun 13 01:44:18 PM PDT 24
Peak memory	647992 kb
Host	smart-fd19e92c-7fdf-4169-bbb5-6a5a8e7bd918
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1224426885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.1224426885 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/24.kmac_test_vectors_shake_256.1235568382
Short name	T1039
Test name
Test status
Simulation time	574599340014 ps
CPU time	3862.4 seconds
Started	Jun 13 12:38:04 PM PDT 24
Finished	Jun 13 01:42:28 PM PDT 24
Peak memory	551200 kb
Host	smart-661091af-9023-4658-bc47-9ec6e3e02487
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1235568382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1235568382 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/24.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/25.kmac_alert_test.2618232400
Short name	T411
Test name
Test status
Simulation time	13532050 ps
CPU time	0.83 seconds
Started	Jun 13 12:38:14 PM PDT 24
Finished	Jun 13 12:38:16 PM PDT 24
Peak memory	205228 kb
Host	smart-3db109f6-fb04-48be-aa3c-240342d8b51d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618232400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.2618232400 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_alert_test/latest

Test location	/workspace/coverage/default/25.kmac_app.3411348124
Short name	T778
Test name
Test status
Simulation time	5052361058 ps
CPU time	56.75 seconds
Started	Jun 13 12:38:13 PM PDT 24
Finished	Jun 13 12:39:11 PM PDT 24
Peak memory	224936 kb
Host	smart-f9181fa1-9a60-46d5-aeca-d19354bc1d01
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3411348124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.3411348124 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_app/latest

Test location	/workspace/coverage/default/25.kmac_burst_write.302320107
Short name	T980
Test name
Test status
Simulation time	16891751615 ps
CPU time	512.84 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:46:47 PM PDT 24
Peak memory	230400 kb
Host	smart-898fb901-434a-4ac5-ac4f-93b72d2c1d96
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302320107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.302320107 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_burst_write/latest

Test location	/workspace/coverage/default/25.kmac_entropy_refresh.2582630323
Short name	T1056
Test name
Test status
Simulation time	1374956170 ps
CPU time	8.74 seconds
Started	Jun 13 12:38:21 PM PDT 24
Finished	Jun 13 12:38:31 PM PDT 24
Peak memory	215804 kb
Host	smart-4fe6e9cf-2a22-4ca4-ab17-4053b2b9e682
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2582630323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.2582630323 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/25.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/25.kmac_error.2257623421
Short name	T551
Test name
Test status
Simulation time	9345430198 ps
CPU time	54.86 seconds
Started	Jun 13 12:38:13 PM PDT 24
Finished	Jun 13 12:39:09 PM PDT 24
Peak memory	233228 kb
Host	smart-5cc65130-0c91-4021-ab3c-aa384b355ec6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2257623421 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2257623421 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_error/latest

Test location	/workspace/coverage/default/25.kmac_key_error.415417259
Short name	T733
Test name
Test status
Simulation time	411718219 ps
CPU time	2.54 seconds
Started	Jun 13 12:38:14 PM PDT 24
Finished	Jun 13 12:38:17 PM PDT 24
Peak memory	207332 kb
Host	smart-f69e3fff-e291-41b1-8d74-786713fd39ed
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=415417259 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.415417259 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_key_error/latest

Test location	/workspace/coverage/default/25.kmac_lc_escalation.2749452495
Short name	T38
Test name
Test status
Simulation time	453381986 ps
CPU time	11.31 seconds
Started	Jun 13 12:38:18 PM PDT 24
Finished	Jun 13 12:38:30 PM PDT 24
Peak memory	223948 kb
Host	smart-5ae0bdaf-1426-4f1b-a7f3-457a9961eccb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749452495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.2749452495 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/25.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/25.kmac_long_msg_and_output.2929233639
Short name	T276
Test name
Test status
Simulation time	14420425021 ps
CPU time	1069.88 seconds
Started	Jun 13 12:38:14 PM PDT 24
Finished	Jun 13 12:56:05 PM PDT 24
Peak memory	347648 kb
Host	smart-07a623a0-6c18-4b18-a51d-1b718418c92b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929233639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a nd_output.2929233639 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/25.kmac_sideload.2706354602
Short name	T1067
Test name
Test status
Simulation time	57326247586 ps
CPU time	377.97 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 12:44:24 PM PDT 24
Peak memory	247220 kb
Host	smart-5855c927-7f02-49f8-9c6e-cd5cc5d4a871
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706354602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2706354602 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_sideload/latest

Test location	/workspace/coverage/default/25.kmac_smoke.125130533
Short name	T41
Test name
Test status
Simulation time	1258302903 ps
CPU time	9.18 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 12:38:20 PM PDT 24
Peak memory	223908 kb
Host	smart-0751a418-c991-4159-8881-1b8a188ab72f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=125130533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.125130533 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_smoke/latest

Test location	/workspace/coverage/default/25.kmac_stress_all.836508645
Short name	T862
Test name
Test status
Simulation time	28265781788 ps
CPU time	922.05 seconds
Started	Jun 13 12:38:15 PM PDT 24
Finished	Jun 13 12:53:38 PM PDT 24
Peak memory	355556 kb
Host	smart-e3cfdb43-f00e-4154-b654-772ccc258f4c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=836508645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.836508645 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_stress_all/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac.721224949
Short name	T553
Test name
Test status
Simulation time	335147223 ps
CPU time	4.74 seconds
Started	Jun 13 12:38:05 PM PDT 24
Finished	Jun 13 12:38:11 PM PDT 24
Peak memory	215812 kb
Host	smart-31ca9842-e82a-494e-a768-4cb1c6b40ced
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721224949 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 25.kmac_test_vectors_kmac.721224949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_kmac_xof.753391094
Short name	T484
Test name
Test status
Simulation time	67148449 ps
CPU time	4.04 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:16 PM PDT 24
Peak memory	215788 kb
Host	smart-bdc5aa1d-02d1-4857-981d-9e69c08fd187
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753391094 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 25.kmac_test_vectors_kmac_xof.753391094 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_224.3681982960
Short name	T469
Test name
Test status
Simulation time	337282613712 ps
CPU time	1838.46 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 01:08:50 PM PDT 24
Peak memory	394888 kb
Host	smart-5ad17b01-9fdb-48e9-ac9a-941f40b39271
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3681982960 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3681982960 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_256.1984029817
Short name	T807
Test name
Test status
Simulation time	81249825090 ps
CPU time	1664.88 seconds
Started	Jun 13 12:38:11 PM PDT 24
Finished	Jun 13 01:05:56 PM PDT 24
Peak memory	371720 kb
Host	smart-a367694f-7654-49f5-8789-66797e7559d8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1984029817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.1984029817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_384.3750678419
Short name	T843
Test name
Test status
Simulation time	14199478953 ps
CPU time	1125.2 seconds
Started	Jun 13 12:38:16 PM PDT 24
Finished	Jun 13 12:57:02 PM PDT 24
Peak memory	334884 kb
Host	smart-9fef8fac-86b0-498f-82e2-d72401de72a8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3750678419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.3750678419 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_sha3_512.2211471760
Short name	T985
Test name
Test status
Simulation time	104092258351 ps
CPU time	776.13 seconds
Started	Jun 13 12:38:11 PM PDT 24
Finished	Jun 13 12:51:08 PM PDT 24
Peak memory	292012 kb
Host	smart-be042e99-b23f-4af9-b6c9-4b70b25ebaeb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2211471760 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.2211471760 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_128.3038971021
Short name	T1
Test name
Test status
Simulation time	917773156026 ps
CPU time	5324.97 seconds
Started	Jun 13 12:38:09 PM PDT 24
Finished	Jun 13 02:06:55 PM PDT 24
Peak memory	651448 kb
Host	smart-78f80d52-153b-4919-860f-b3d24d2d56db
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3038971021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.3038971021 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/25.kmac_test_vectors_shake_256.2091811432
Short name	T467
Test name
Test status
Simulation time	44653925920 ps
CPU time	3369.03 seconds
Started	Jun 13 12:38:15 PM PDT 24
Finished	Jun 13 01:34:25 PM PDT 24
Peak memory	553996 kb
Host	smart-0bb3b73f-6a60-495d-9c81-b9c0ee4c9328
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2091811432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.2091811432 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/25.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/26.kmac_alert_test.1452590743
Short name	T852
Test name
Test status
Simulation time	73699744 ps
CPU time	0.81 seconds
Started	Jun 13 12:38:19 PM PDT 24
Finished	Jun 13 12:38:20 PM PDT 24
Peak memory	205152 kb
Host	smart-6ae00b5b-9b0c-4937-b116-e38d424a4a3f
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452590743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.1452590743 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_alert_test/latest

Test location	/workspace/coverage/default/26.kmac_app.1863880246
Short name	T93
Test name
Test status
Simulation time	75020746673 ps
CPU time	253.74 seconds
Started	Jun 13 12:38:23 PM PDT 24
Finished	Jun 13 12:42:37 PM PDT 24
Peak memory	243532 kb
Host	smart-4585f212-d783-4441-b9c4-c2014fcb6cba
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1863880246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.1863880246 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_app/latest

Test location	/workspace/coverage/default/26.kmac_burst_write.2459106726
Short name	T558
Test name
Test status
Simulation time	8848030179 ps
CPU time	764.44 seconds
Started	Jun 13 12:38:14 PM PDT 24
Finished	Jun 13 12:51:00 PM PDT 24
Peak memory	233232 kb
Host	smart-36a2d6cf-904b-4094-8b3a-b1873d6f22da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2459106726 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.2459106726 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_burst_write/latest

Test location	/workspace/coverage/default/26.kmac_entropy_refresh.2386235106
Short name	T644
Test name
Test status
Simulation time	42546079 ps
CPU time	2.68 seconds
Started	Jun 13 12:38:20 PM PDT 24
Finished	Jun 13 12:38:23 PM PDT 24
Peak memory	216860 kb
Host	smart-e127537c-a116-487e-a843-7d4218f46157
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2386235106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.2386235106 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/26.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/26.kmac_error.153305668
Short name	T388
Test name
Test status
Simulation time	1986797858 ps
CPU time	127.73 seconds
Started	Jun 13 12:38:25 PM PDT 24
Finished	Jun 13 12:40:33 PM PDT 24
Peak memory	240340 kb
Host	smart-82158112-dcbb-4dbb-9f36-61d4737650c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=153305668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.153305668 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_error/latest

Test location	/workspace/coverage/default/26.kmac_key_error.1523898270
Short name	T705
Test name
Test status
Simulation time	213668935 ps
CPU time	1.75 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:38:29 PM PDT 24
Peak memory	207404 kb
Host	smart-cb9386ec-7550-4b5a-88a9-465709c07413
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1523898270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.1523898270 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_key_error/latest

Test location	/workspace/coverage/default/26.kmac_lc_escalation.3594124154
Short name	T600
Test name
Test status
Simulation time	46344312 ps
CPU time	1.39 seconds
Started	Jun 13 12:38:24 PM PDT 24
Finished	Jun 13 12:38:27 PM PDT 24
Peak memory	215696 kb
Host	smart-d281e3d2-5975-497e-b673-c5bafc19aa07
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3594124154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3594124154 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/26.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/26.kmac_long_msg_and_output.3803870901
Short name	T989
Test name
Test status
Simulation time	166472891353 ps
CPU time	262.5 seconds
Started	Jun 13 12:38:18 PM PDT 24
Finished	Jun 13 12:42:41 PM PDT 24
Peak memory	235676 kb
Host	smart-7dc862e8-cc84-403f-ad99-52c14b154b95
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803870901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a nd_output.3803870901 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/26.kmac_sideload.1704162395
Short name	T693
Test name
Test status
Simulation time	2910568887 ps
CPU time	76.37 seconds
Started	Jun 13 12:38:13 PM PDT 24
Finished	Jun 13 12:39:31 PM PDT 24
Peak memory	227100 kb
Host	smart-e4586083-0bf8-43af-97ca-20ab99773946
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704162395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.1704162395 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_sideload/latest

Test location	/workspace/coverage/default/26.kmac_smoke.1926580802
Short name	T1072
Test name
Test status
Simulation time	834758101 ps
CPU time	46.77 seconds
Started	Jun 13 12:38:13 PM PDT 24
Finished	Jun 13 12:39:01 PM PDT 24
Peak memory	218912 kb
Host	smart-a7a3a98e-faa7-4e2a-b7d6-19f83a18e1e3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1926580802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.1926580802 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_smoke/latest

Test location	/workspace/coverage/default/26.kmac_stress_all.2792511552
Short name	T959
Test name
Test status
Simulation time	19055529468 ps
CPU time	161.91 seconds
Started	Jun 13 12:38:19 PM PDT 24
Finished	Jun 13 12:41:02 PM PDT 24
Peak memory	249820 kb
Host	smart-af4d567d-bbc5-4019-a7c1-cc97e574bcaa
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2792511552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.2792511552 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_stress_all/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac.2642533288
Short name	T783
Test name
Test status
Simulation time	1353961875 ps
CPU time	4.79 seconds
Started	Jun 13 12:38:21 PM PDT 24
Finished	Jun 13 12:38:26 PM PDT 24
Peak memory	215840 kb
Host	smart-89c383f1-6ad7-47d8-99f0-39fb8a3b0205
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642533288 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 26.kmac_test_vectors_kmac.2642533288 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_kmac_xof.3822588720
Short name	T882
Test name
Test status
Simulation time	176652376 ps
CPU time	4.68 seconds
Started	Jun 13 12:38:20 PM PDT 24
Finished	Jun 13 12:38:25 PM PDT 24
Peak memory	215792 kb
Host	smart-ac72cb6d-7605-45c0-be87-e63bac0abb87
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822588720 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_kmac_xof.3822588720 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_224.2300225708
Short name	T784
Test name
Test status
Simulation time	85723435725 ps
CPU time	1679.27 seconds
Started	Jun 13 12:38:11 PM PDT 24
Finished	Jun 13 01:06:11 PM PDT 24
Peak memory	372704 kb
Host	smart-2067b61a-24e4-4e61-a74c-c0166f061fa4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2300225708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.2300225708 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_256.2754692334
Short name	T209
Test name
Test status
Simulation time	95567214706 ps
CPU time	1825.17 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 01:08:38 PM PDT 24
Peak memory	375344 kb
Host	smart-605e9f41-728f-4d06-8d95-8a37e9fcb1b7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2754692334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_256.2754692334 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_384.2250934553
Short name	T854
Test name
Test status
Simulation time	1205436127857 ps
CPU time	1286.14 seconds
Started	Jun 13 12:38:25 PM PDT 24
Finished	Jun 13 12:59:52 PM PDT 24
Peak memory	332740 kb
Host	smart-b252c761-73fa-42ad-b7ab-46ded7dc84c1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2250934553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.2250934553 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_sha3_512.1213444828
Short name	T447
Test name
Test status
Simulation time	210968728426 ps
CPU time	962.39 seconds
Started	Jun 13 12:38:23 PM PDT 24
Finished	Jun 13 12:54:26 PM PDT 24
Peak memory	293240 kb
Host	smart-472a0e16-72f7-4212-baa7-8769ffebeb2e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1213444828 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1213444828 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_128.2679817601
Short name	T366
Test name
Test status
Simulation time	716091372639 ps
CPU time	5086.81 seconds
Started	Jun 13 12:38:18 PM PDT 24
Finished	Jun 13 02:03:06 PM PDT 24
Peak memory	650532 kb
Host	smart-3cd23fd9-6241-480c-8ae7-9900b29e8f16
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2679817601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2679817601 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/26.kmac_test_vectors_shake_256.1759834097
Short name	T244
Test name
Test status
Simulation time	270149786987 ps
CPU time	3275.37 seconds
Started	Jun 13 12:38:24 PM PDT 24
Finished	Jun 13 01:33:00 PM PDT 24
Peak memory	559836 kb
Host	smart-31d3bdf4-4f8a-4a86-bcd6-6a6668995e6f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1759834097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.1759834097 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/26.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/27.kmac_alert_test.2900983222
Short name	T951
Test name
Test status
Simulation time	15460933 ps
CPU time	0.84 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 12:38:32 PM PDT 24
Peak memory	205200 kb
Host	smart-969d6b4c-6e08-41f5-995f-6a8f2f1426b9
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900983222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2900983222 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_alert_test/latest

Test location	/workspace/coverage/default/27.kmac_app.3377029160
Short name	T434
Test name
Test status
Simulation time	2654898807 ps
CPU time	70.62 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:39:38 PM PDT 24
Peak memory	227544 kb
Host	smart-7310188c-aad6-4322-b7aa-e0585c4d61f6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3377029160 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.3377029160 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_app/latest

Test location	/workspace/coverage/default/27.kmac_burst_write.973944855
Short name	T476
Test name
Test status
Simulation time	9210577945 ps
CPU time	206.51 seconds
Started	Jun 13 12:38:24 PM PDT 24
Finished	Jun 13 12:41:52 PM PDT 24
Peak memory	225228 kb
Host	smart-2aa1cd10-4e43-4207-9c36-4fe7e23f807b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=973944855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.973944855 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_burst_write/latest

Test location	/workspace/coverage/default/27.kmac_entropy_refresh.207008178
Short name	T588
Test name
Test status
Simulation time	13683387301 ps
CPU time	106.82 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:40:14 PM PDT 24
Peak memory	230808 kb
Host	smart-ffa0fd1a-901b-4eee-a3c3-ba0b61ac2967
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=207008178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.207008178 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/27.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/27.kmac_error.440515252
Short name	T972
Test name
Test status
Simulation time	18285866409 ps
CPU time	229.36 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 12:42:19 PM PDT 24
Peak memory	256692 kb
Host	smart-8d7f9bd8-adba-4799-bade-9bf656024d00
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=440515252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.440515252 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_error/latest

Test location	/workspace/coverage/default/27.kmac_key_error.1695054641
Short name	T765
Test name
Test status
Simulation time	925739591 ps
CPU time	5.49 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	207372 kb
Host	smart-f697bc87-ed86-4f9b-90b2-fa60e7ce924f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695054641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.1695054641 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_key_error/latest

Test location	/workspace/coverage/default/27.kmac_lc_escalation.929866271
Short name	T606
Test name
Test status
Simulation time	9538728582 ps
CPU time	25.55 seconds
Started	Jun 13 12:38:25 PM PDT 24
Finished	Jun 13 12:38:52 PM PDT 24
Peak memory	228952 kb
Host	smart-6fa2846f-5c73-4858-a84c-ac15d1295f95
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=929866271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.929866271 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/27.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/27.kmac_long_msg_and_output.1532275142
Short name	T694
Test name
Test status
Simulation time	6424448712 ps
CPU time	205.51 seconds
Started	Jun 13 12:38:22 PM PDT 24
Finished	Jun 13 12:41:48 PM PDT 24
Peak memory	240416 kb
Host	smart-38603b08-e44c-4b0d-a7a8-2880a2a4b659
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532275142 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_a nd_output.1532275142 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/27.kmac_sideload.3699955393
Short name	T716
Test name
Test status
Simulation time	2903806008 ps
CPU time	243.76 seconds
Started	Jun 13 12:38:18 PM PDT 24
Finished	Jun 13 12:42:22 PM PDT 24
Peak memory	241780 kb
Host	smart-8b17d37c-5683-40d4-b1a7-8a135981daf5
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699955393 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.3699955393 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_sideload/latest

Test location	/workspace/coverage/default/27.kmac_smoke.225334970
Short name	T871
Test name
Test status
Simulation time	1241522206 ps
CPU time	15.39 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:38:42 PM PDT 24
Peak memory	216856 kb
Host	smart-a3157bf3-05c0-43cb-86ff-50c70a478be3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=225334970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.225334970 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_smoke/latest

Test location	/workspace/coverage/default/27.kmac_stress_all.1191900464
Short name	T736
Test name
Test status
Simulation time	406292046480 ps
CPU time	2821.02 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 01:25:28 PM PDT 24
Peak memory	527452 kb
Host	smart-a1f633d5-e9a3-4a4b-923c-d86bf47f3386
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1191900464 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.1191900464 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_stress_all/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac.3400019490
Short name	T202
Test name
Test status
Simulation time	69545103 ps
CPU time	4.29 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	215760 kb
Host	smart-e3ecfc32-7c64-498c-800b-4ae1898b03ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400019490 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 27.kmac_test_vectors_kmac.3400019490 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_kmac_xof.2643972468
Short name	T964
Test name
Test status
Simulation time	953426239 ps
CPU time	4.42 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	215776 kb
Host	smart-d9fb0450-f686-4448-b1c4-684ab0e54c8e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643972468 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_kmac_xof.2643972468 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_224.1094392335
Short name	T892
Test name
Test status
Simulation time	40153478445 ps
CPU time	1547.13 seconds
Started	Jun 13 12:38:21 PM PDT 24
Finished	Jun 13 01:04:09 PM PDT 24
Peak memory	393232 kb
Host	smart-accbbf04-ef94-4899-bf80-96d8e984045c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1094392335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1094392335 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_256.103477412
Short name	T453
Test name
Test status
Simulation time	18861470846 ps
CPU time	1451.13 seconds
Started	Jun 13 12:38:20 PM PDT 24
Finished	Jun 13 01:02:31 PM PDT 24
Peak memory	377684 kb
Host	smart-4be11ed0-b313-4d79-a756-b8d598e0b4d4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=103477412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.103477412 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_384.732084550
Short name	T190
Test name
Test status
Simulation time	579705029650 ps
CPU time	1561.14 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 01:04:32 PM PDT 24
Peak memory	332884 kb
Host	smart-b1fdae84-9f5b-4e3e-abe1-37df2f1e2f3b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=732084550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.732084550 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_sha3_512.1949491389
Short name	T175
Test name
Test status
Simulation time	37370190629 ps
CPU time	920.9 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:53:48 PM PDT 24
Peak memory	296856 kb
Host	smart-352e3b2d-879d-47ba-8abb-2e82bfdb984a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1949491389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1949491389 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_128.4210988449
Short name	T646
Test name
Test status
Simulation time	86784066190 ps
CPU time	4080.48 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 01:46:32 PM PDT 24
Peak memory	640728 kb
Host	smart-1a9a5a86-2a77-4d00-8441-83535d9a475b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4210988449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.4210988449 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/27.kmac_test_vectors_shake_256.1662375313
Short name	T845
Test name
Test status
Simulation time	606129609720 ps
CPU time	4001.86 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 01:45:12 PM PDT 24
Peak memory	562148 kb
Host	smart-17e6d52c-648b-405b-aba2-e4364abdde61
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1662375313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.1662375313 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/27.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/28.kmac_alert_test.397596420
Short name	T305
Test name
Test status
Simulation time	23579602 ps
CPU time	0.82 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	205228 kb
Host	smart-691930fa-6920-4ccd-abc4-b6088c808e78
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397596420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.397596420 +enable_m asking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_alert_test/latest

Test location	/workspace/coverage/default/28.kmac_app.603656027
Short name	T114
Test name
Test status
Simulation time	8492869331 ps
CPU time	127.75 seconds
Started	Jun 13 12:38:25 PM PDT 24
Finished	Jun 13 12:40:34 PM PDT 24
Peak memory	235068 kb
Host	smart-576888dd-c2fa-4244-ae9c-3e58409c00e1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=603656027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.603656027 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_app/latest

Test location	/workspace/coverage/default/28.kmac_burst_write.1923378235
Short name	T1047
Test name
Test status
Simulation time	1812112441 ps
CPU time	53.27 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 12:39:23 PM PDT 24
Peak memory	218976 kb
Host	smart-39dd6f39-66b4-409f-b72d-1d79e11a317f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1923378235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.1923378235 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_burst_write/latest

Test location	/workspace/coverage/default/28.kmac_entropy_refresh.3165520264
Short name	T278
Test name
Test status
Simulation time	4516602708 ps
CPU time	75.78 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:39:44 PM PDT 24
Peak memory	227272 kb
Host	smart-95f9a1af-cd0a-4b60-8659-11bb542b9027
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3165520264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.3165520264 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/28.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/28.kmac_error.1170336045
Short name	T412
Test name
Test status
Simulation time	1556371481 ps
CPU time	78.73 seconds
Started	Jun 13 12:38:25 PM PDT 24
Finished	Jun 13 12:39:45 PM PDT 24
Peak memory	240360 kb
Host	smart-149f33cf-67aa-4980-8590-f74f8a96b763
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1170336045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1170336045 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_error/latest

Test location	/workspace/coverage/default/28.kmac_key_error.3766169304
Short name	T896
Test name
Test status
Simulation time	502038262 ps
CPU time	3.32 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	207444 kb
Host	smart-b9b6ca1a-eda3-4e9e-b925-cb455b517f24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3766169304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3766169304 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_key_error/latest

Test location	/workspace/coverage/default/28.kmac_lc_escalation.1231720598
Short name	T639
Test name
Test status
Simulation time	46900838 ps
CPU time	1.29 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 12:38:28 PM PDT 24
Peak memory	215768 kb
Host	smart-782d978b-9695-4fac-81f4-11104e3973a6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1231720598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.1231720598 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/28.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/28.kmac_long_msg_and_output.819622665
Short name	T948
Test name
Test status
Simulation time	57930472720 ps
CPU time	311.22 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 12:43:42 PM PDT 24
Peak memory	248016 kb
Host	smart-ae9edca3-df7a-4371-af4f-588e595d7381
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819622665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_an d_output.819622665 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/28.kmac_sideload.1931858594
Short name	T391
Test name
Test status
Simulation time	1943558588 ps
CPU time	154.45 seconds
Started	Jun 13 12:38:30 PM PDT 24
Finished	Jun 13 12:41:06 PM PDT 24
Peak memory	231596 kb
Host	smart-5def35aa-c1dc-4b2c-9961-c8bc15e49833
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931858594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.1931858594 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_sideload/latest

Test location	/workspace/coverage/default/28.kmac_smoke.2485149352
Short name	T508
Test name
Test status
Simulation time	3340808489 ps
CPU time	41.52 seconds
Started	Jun 13 12:38:30 PM PDT 24
Finished	Jun 13 12:39:14 PM PDT 24
Peak memory	223960 kb
Host	smart-1d697289-24c6-4517-92af-ccbadd759e03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2485149352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.2485149352 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_smoke/latest

Test location	/workspace/coverage/default/28.kmac_stress_all.1874596184
Short name	T712
Test name
Test status
Simulation time	52815391309 ps
CPU time	1104.02 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 12:56:55 PM PDT 24
Peak memory	351972 kb
Host	smart-bfeab104-3bce-46fc-bf0f-20a3afd30e70
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1874596184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.1874596184 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_stress_all/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac.3983088500
Short name	T995
Test name
Test status
Simulation time	125670371 ps
CPU time	3.92 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	215820 kb
Host	smart-c14c4768-a1f0-4050-a66b-3674ac9f7a69
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983088500 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 28.kmac_test_vectors_kmac.3983088500 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_kmac_xof.3813187674
Short name	T312
Test name
Test status
Simulation time	388635265 ps
CPU time	4.33 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	215780 kb
Host	smart-eb0f94bd-28ba-41cc-86f7-6db8f0212e7a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813187674 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_kmac_xof.3813187674 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_224.3725047998
Short name	T348
Test name
Test status
Simulation time	69923131302 ps
CPU time	1724.91 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 01:07:13 PM PDT 24
Peak memory	396872 kb
Host	smart-ca894e09-7c5b-414a-9084-86897ddd6c46
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3725047998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3725047998 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_256.959829320
Short name	T548
Test name
Test status
Simulation time	161025064925 ps
CPU time	1677.51 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 01:06:28 PM PDT 24
Peak memory	386792 kb
Host	smart-77e3b809-63c1-42ba-b048-3c6682af5419
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=959829320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.959829320 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_384.1217214132
Short name	T206
Test name
Test status
Simulation time	301439984641 ps
CPU time	1312.49 seconds
Started	Jun 13 12:38:26 PM PDT 24
Finished	Jun 13 01:00:20 PM PDT 24
Peak memory	331648 kb
Host	smart-237b0671-6a7f-4ffb-90b6-dcc81ae4250d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1217214132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.1217214132 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_sha3_512.749672584
Short name	T855
Test name
Test status
Simulation time	39279810561 ps
CPU time	779.92 seconds
Started	Jun 13 12:38:29 PM PDT 24
Finished	Jun 13 12:51:31 PM PDT 24
Peak memory	293052 kb
Host	smart-ff6c53f0-7bb9-4c6e-95c1-5d0452a0d4f3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=749672584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.749672584 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_128.1942771581
Short name	T564
Test name
Test status
Simulation time	52479083811 ps
CPU time	4016.82 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 01:45:25 PM PDT 24
Peak memory	640644 kb
Host	smart-c190502f-7c28-47c1-849b-8f0feb10f5ab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1942771581 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.1942771581 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/28.kmac_test_vectors_shake_256.1943116574
Short name	T246
Test name
Test status
Simulation time	152958916222 ps
CPU time	4016.22 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 01:45:27 PM PDT 24
Peak memory	561596 kb
Host	smart-d776a8c6-f4aa-4350-b74c-ff03fbbc3aee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1943116574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.1943116574 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/28.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/29.kmac_alert_test.1377446662
Short name	T890
Test name
Test status
Simulation time	51412275 ps
CPU time	0.84 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:38:34 PM PDT 24
Peak memory	205064 kb
Host	smart-ea22e7ee-66a3-4c6c-9208-68e10911c17d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377446662 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.1377446662 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_alert_test/latest

Test location	/workspace/coverage/default/29.kmac_app.3990976198
Short name	T194
Test name
Test status
Simulation time	37240674836 ps
CPU time	230.7 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 12:42:24 PM PDT 24
Peak memory	242488 kb
Host	smart-1fcc2c5a-eb43-4c84-97af-ea8e688a2474
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3990976198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.3990976198 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_app/latest

Test location	/workspace/coverage/default/29.kmac_burst_write.3896159976
Short name	T597
Test name
Test status
Simulation time	8166002312 ps
CPU time	709.62 seconds
Started	Jun 13 12:38:30 PM PDT 24
Finished	Jun 13 12:50:22 PM PDT 24
Peak memory	232464 kb
Host	smart-daa796e5-a907-4bcb-81db-c42a8f6a0b99
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3896159976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.3896159976 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_burst_write/latest

Test location	/workspace/coverage/default/29.kmac_entropy_refresh.2446583668
Short name	T263
Test name
Test status
Simulation time	21737939902 ps
CPU time	81.99 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:39:55 PM PDT 24
Peak memory	235836 kb
Host	smart-4e2edabc-5dd7-4b0d-b20a-08e4efd3df2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2446583668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.2446583668 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/29.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/29.kmac_error.1915724790
Short name	T437
Test name
Test status
Simulation time	42848594141 ps
CPU time	409.81 seconds
Started	Jun 13 12:38:30 PM PDT 24
Finished	Jun 13 12:45:22 PM PDT 24
Peak memory	271416 kb
Host	smart-f83c6c42-2683-4cd9-ad8a-b0a42dbcc819
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1915724790 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1915724790 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_error/latest

Test location	/workspace/coverage/default/29.kmac_key_error.2501757258
Short name	T900
Test name
Test status
Simulation time	1331456820 ps
CPU time	6.73 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:38:39 PM PDT 24
Peak memory	215736 kb
Host	smart-4200bbb3-b4d0-4be1-9116-f31b3e6e99b0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2501757258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.2501757258 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_key_error/latest

Test location	/workspace/coverage/default/29.kmac_lc_escalation.3707527005
Short name	T295
Test name
Test status
Simulation time	50411479 ps
CPU time	1.36 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:38:34 PM PDT 24
Peak memory	215672 kb
Host	smart-9a80e03d-63ac-4bc1-8770-4e775ea3a738
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3707527005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.3707527005 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/29.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/29.kmac_long_msg_and_output.1215640747
Short name	T934
Test name
Test status
Simulation time	396160657921 ps
CPU time	935 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:54:07 PM PDT 24
Peak memory	303852 kb
Host	smart-2e6d184a-93f8-487d-9f5b-c8a63acbcb7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215640747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a nd_output.1215640747 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/29.kmac_sideload.4155430598
Short name	T673
Test name
Test status
Simulation time	12353453347 ps
CPU time	78.81 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 12:39:53 PM PDT 24
Peak memory	227144 kb
Host	smart-11981ef7-7298-4963-809d-79320f24c968
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155430598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.4155430598 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_sideload/latest

Test location	/workspace/coverage/default/29.kmac_smoke.899697699
Short name	T1004
Test name
Test status
Simulation time	2182563215 ps
CPU time	32.97 seconds
Started	Jun 13 12:38:30 PM PDT 24
Finished	Jun 13 12:39:04 PM PDT 24
Peak memory	220688 kb
Host	smart-33ec563f-d411-464f-ab89-c4ff2163a218
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=899697699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.899697699 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_smoke/latest

Test location	/workspace/coverage/default/29.kmac_stress_all.13419251
Short name	T466
Test name
Test status
Simulation time	121224864757 ps
CPU time	1728.75 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 01:07:22 PM PDT 24
Peak memory	400564 kb
Host	smart-24b20127-3a14-458c-a07d-34eaf8ccecb6
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=13419251 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.13419251 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all/latest

Test location	/workspace/coverage/default/29.kmac_stress_all_with_rand_reset.3788317412
Short name	T1000
Test name
Test status
Simulation time	93481313353 ps
CPU time	933.13 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:54:06 PM PDT 24
Peak memory	289976 kb
Host	smart-aa841e73-c60d-4667-bb3d-125743cad7cd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3788317412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all_with_rand_reset.3788317412 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac.4256839389
Short name	T591
Test name
Test status
Simulation time	450403020 ps
CPU time	4.72 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 12:38:39 PM PDT 24
Peak memory	208916 kb
Host	smart-48de4643-3ab5-48e4-86ce-7d147f5f7c91
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256839389 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 29.kmac_test_vectors_kmac.4256839389 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_kmac_xof.2989224939
Short name	T633
Test name
Test status
Simulation time	70744116 ps
CPU time	3.8 seconds
Started	Jun 13 12:38:33 PM PDT 24
Finished	Jun 13 12:38:38 PM PDT 24
Peak memory	215768 kb
Host	smart-d043b2da-702b-4a6b-b9f4-33de413d299d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989224939 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_kmac_xof.2989224939 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_224.2238148957
Short name	T1086
Test name
Test status
Simulation time	40036704494 ps
CPU time	1527.34 seconds
Started	Jun 13 12:38:34 PM PDT 24
Finished	Jun 13 01:04:02 PM PDT 24
Peak memory	391904 kb
Host	smart-af8e0933-ccfe-4765-a338-b3142208da4b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2238148957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2238148957 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_256.2938099213
Short name	T273
Test name
Test status
Simulation time	18437635030 ps
CPU time	1390.32 seconds
Started	Jun 13 12:38:33 PM PDT 24
Finished	Jun 13 01:01:45 PM PDT 24
Peak memory	373424 kb
Host	smart-92d6b195-86bf-4468-b368-cc307170fe24
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2938099213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.2938099213 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_384.2007618392
Short name	T224
Test name
Test status
Simulation time	192195454330 ps
CPU time	1214.04 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:58:46 PM PDT 24
Peak memory	329916 kb
Host	smart-0e3a982f-91c1-432a-b4f1-1a527dda600a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2007618392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.2007618392 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_sha3_512.140580284
Short name	T297
Test name
Test status
Simulation time	42040762756 ps
CPU time	878.46 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 12:53:11 PM PDT 24
Peak memory	292056 kb
Host	smart-6249aa35-2abe-4fa7-b3f7-0639f6cbcdce
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=140580284 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.140580284 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_128.1714592262
Short name	T792
Test name
Test status
Simulation time	241753735540 ps
CPU time	3953.75 seconds
Started	Jun 13 12:38:32 PM PDT 24
Finished	Jun 13 01:44:27 PM PDT 24
Peak memory	648072 kb
Host	smart-54d25b88-ccef-4e24-af39-969a39cd134c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1714592262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.1714592262 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/29.kmac_test_vectors_shake_256.2618565876
Short name	T327
Test name
Test status
Simulation time	856505252389 ps
CPU time	4344.62 seconds
Started	Jun 13 12:38:31 PM PDT 24
Finished	Jun 13 01:50:57 PM PDT 24
Peak memory	551180 kb
Host	smart-927712f5-8978-4969-b401-4a926c63a2ac
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2618565876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.2618565876 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/29.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/3.kmac_alert_test.1649965432
Short name	T315
Test name
Test status
Simulation time	47380991 ps
CPU time	0.85 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	204680 kb
Host	smart-bd29dc2a-0368-44e1-8f8b-79d8bc24eca1
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649965432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1649965432 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_alert_test/latest

Test location	/workspace/coverage/default/3.kmac_app.2362797654
Short name	T109
Test name
Test status
Simulation time	8636931784 ps
CPU time	212 seconds
Started	Jun 13 12:36:53 PM PDT 24
Finished	Jun 13 12:40:28 PM PDT 24
Peak memory	239512 kb
Host	smart-d933eb94-b76c-4650-8716-c93b0aeeaf85
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2362797654 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.2362797654 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_app/latest

Test location	/workspace/coverage/default/3.kmac_app_with_partial_data.2784682191
Short name	T365
Test name
Test status
Simulation time	1873852125 ps
CPU time	21.77 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:37:16 PM PDT 24
Peak memory	220692 kb
Host	smart-9c023b21-ddf5-4e2d-9b4a-396a737b803a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2784682191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2784682191 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/3.kmac_burst_write.1189930330
Short name	T43
Test name
Test status
Simulation time	2108118199 ps
CPU time	177.57 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:40:23 PM PDT 24
Peak memory	224528 kb
Host	smart-17ed292f-256d-48cd-9f29-f395d63043c4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1189930330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.1189930330 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_burst_write/latest

Test location	/workspace/coverage/default/3.kmac_edn_timeout_error.2330416153
Short name	T416
Test name
Test status
Simulation time	6356098546 ps
CPU time	31.53 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:37:49 PM PDT 24
Peak memory	220632 kb
Host	smart-163877b4-cc56-4b70-94f9-4349f7f48867
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2330416153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2330416153 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_mode_error.347497458
Short name	T627
Test name
Test status
Simulation time	5765115125 ps
CPU time	27.34 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:41 PM PDT 24
Peak memory	223404 kb
Host	smart-664c595a-c667-463a-b78c-1dc55868c61d
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=347497458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.347497458 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_ready_error.1193350092
Short name	T49
Test name
Test status
Simulation time	32748530757 ps
CPU time	77.59 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:38:38 PM PDT 24
Peak memory	215884 kb
Host	smart-37606bf5-d638-4799-af97-cd9916529bd8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1193350092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1193350092 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/3.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/3.kmac_entropy_refresh.1142073063
Short name	T27
Test name
Test status
Simulation time	19219933300 ps
CPU time	221.81 seconds
Started	Jun 13 12:36:59 PM PDT 24
Finished	Jun 13 12:40:42 PM PDT 24
Peak memory	242364 kb
Host	smart-a2caa054-b888-494f-b416-a3d3e9ced225
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1142073063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.1142073063 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/3.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/3.kmac_error.1921665775
Short name	T290
Test name
Test status
Simulation time	72324332800 ps
CPU time	409.11 seconds
Started	Jun 13 12:36:49 PM PDT 24
Finished	Jun 13 12:43:42 PM PDT 24
Peak memory	253564 kb
Host	smart-f14b472a-1600-41c6-a9ab-5da7bf0e68f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1921665775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.1921665775 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_error/latest

Test location	/workspace/coverage/default/3.kmac_key_error.1619960858
Short name	T773
Test name
Test status
Simulation time	895851924 ps
CPU time	2.19 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:37:12 PM PDT 24
Peak memory	207480 kb
Host	smart-e8b60325-2d06-4cc2-8bdb-43efc24d014b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1619960858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1619960858 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_key_error/latest

Test location	/workspace/coverage/default/3.kmac_lc_escalation.398323983
Short name	T563
Test name
Test status
Simulation time	983454213 ps
CPU time	16.91 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:30 PM PDT 24
Peak memory	223572 kb
Host	smart-cd8043ca-6e66-41e3-8b96-47dfd3c1ac63
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=398323983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.398323983 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/3.kmac_long_msg_and_output.3820132132
Short name	T472
Test name
Test status
Simulation time	1681122544200 ps
CPU time	2448.2 seconds
Started	Jun 13 12:36:53 PM PDT 24
Finished	Jun 13 01:17:45 PM PDT 24
Peak memory	470456 kb
Host	smart-d1da5b9a-f7d5-4e0a-ad25-4a5d365adb7d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820132132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an d_output.3820132132 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/3.kmac_mubi.600000865
Short name	T971
Test name
Test status
Simulation time	1742500053 ps
CPU time	106.07 seconds
Started	Jun 13 12:36:58 PM PDT 24
Finished	Jun 13 12:38:45 PM PDT 24
Peak memory	230932 kb
Host	smart-11acf127-e88a-469e-b2ba-49819e3c9ddd
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=600000865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.600000865 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_mubi/latest

Test location	/workspace/coverage/default/3.kmac_sec_cm.3493751368
Short name	T67
Test name
Test status
Simulation time	7614228958 ps
CPU time	53.16 seconds
Started	Jun 13 12:37:06 PM PDT 24
Finished	Jun 13 12:38:00 PM PDT 24
Peak memory	255792 kb
Host	smart-6068a2e5-4af0-4c69-bc58-faf2273e3767
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493751368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.3493751368 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/3.kmac_sec_cm/latest

Test location	/workspace/coverage/default/3.kmac_sideload.3682725020
Short name	T420
Test name
Test status
Simulation time	4561915418 ps
CPU time	198.98 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:40:29 PM PDT 24
Peak memory	239784 kb
Host	smart-ca3e2070-1154-4874-9138-ff14c2204990
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682725020 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3682725020 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_sideload/latest

Test location	/workspace/coverage/default/3.kmac_smoke.3199832607
Short name	T247
Test name
Test status
Simulation time	1505630036 ps
CPU time	37.88 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:57 PM PDT 24
Peak memory	221552 kb
Host	smart-0be75960-fac9-4cca-b054-1c7d2e32a54e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199832607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3199832607 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_smoke/latest

Test location	/workspace/coverage/default/3.kmac_stress_all.1821558073
Short name	T511
Test name
Test status
Simulation time	330208730470 ps
CPU time	1061.04 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:54:58 PM PDT 24
Peak memory	330892 kb
Host	smart-e3d1ae36-d197-40f5-ba62-c4772e9fa736
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1821558073 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.1821558073 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_stress_all/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac.908766990
Short name	T637
Test name
Test status
Simulation time	250993618 ps
CPU time	5.27 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:37:19 PM PDT 24
Peak memory	215708 kb
Host	smart-643f448a-c833-43a1-b136-bf81b7f5bf25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908766990 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 3.kmac_test_vectors_kmac.908766990 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3890431949
Short name	T435
Test name
Test status
Simulation time	249980771 ps
CPU time	4.09 seconds
Started	Jun 13 12:36:52 PM PDT 24
Finished	Jun 13 12:36:59 PM PDT 24
Peak memory	215660 kb
Host	smart-20794216-55f9-4007-b60f-149cd43b57e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890431949 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3890431949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_224.430503746
Short name	T208
Test name
Test status
Simulation time	190830606019 ps
CPU time	1811.32 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 01:07:26 PM PDT 24
Peak memory	377516 kb
Host	smart-64821369-eb9e-4927-92ad-d0ff6caee0c9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=430503746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.430503746 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_256.102381021
Short name	T199
Test name
Test status
Simulation time	68767192772 ps
CPU time	1524.98 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 01:02:45 PM PDT 24
Peak memory	377372 kb
Host	smart-0c17c32b-0f20-4288-822c-1c2e9322c80a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=102381021 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.102381021 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_384.2340603319
Short name	T438
Test name
Test status
Simulation time	29466692707 ps
CPU time	1180.44 seconds
Started	Jun 13 12:36:50 PM PDT 24
Finished	Jun 13 12:56:34 PM PDT 24
Peak memory	345144 kb
Host	smart-07c81929-c5bb-4a88-be7a-cd654041520a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2340603319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2340603319 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_sha3_512.1699081933
Short name	T583
Test name
Test status
Simulation time	37667828482 ps
CPU time	746.68 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:49:21 PM PDT 24
Peak memory	292948 kb
Host	smart-7d1971a4-0816-4388-97fe-51796abe1065
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1699081933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.1699081933 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_128.3411091341
Short name	T624
Test name
Test status
Simulation time	108472237573 ps
CPU time	3888.33 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 01:42:02 PM PDT 24
Peak memory	629900 kb
Host	smart-a0060988-88a7-4681-9c43-1d64d3157f9f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3411091341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.3411091341 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/3.kmac_test_vectors_shake_256.138527061
Short name	T757
Test name
Test status
Simulation time	45746922166 ps
CPU time	3598.94 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 01:37:12 PM PDT 24
Peak memory	564580 kb
Host	smart-ff4ae844-b63f-412e-8685-7c353b0c31ee
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=138527061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.138527061 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/3.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/30.kmac_alert_test.2392220392
Short name	T3
Test name
Test status
Simulation time	113482245 ps
CPU time	0.8 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 12:38:47 PM PDT 24
Peak memory	205212 kb
Host	smart-dec37434-df59-47e5-b03e-f13e715cd472
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392220392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.2392220392 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_alert_test/latest

Test location	/workspace/coverage/default/30.kmac_app.3383998211
Short name	T735
Test name
Test status
Simulation time	8272340906 ps
CPU time	34.38 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:39:17 PM PDT 24
Peak memory	223956 kb
Host	smart-9ecb4ac7-6096-402e-b674-adc54d573b2c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3383998211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.3383998211 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_app/latest

Test location	/workspace/coverage/default/30.kmac_burst_write.1604833768
Short name	T120
Test name
Test status
Simulation time	3010572994 ps
CPU time	227.17 seconds
Started	Jun 13 12:38:43 PM PDT 24
Finished	Jun 13 12:42:31 PM PDT 24
Peak memory	225160 kb
Host	smart-1b82edb6-34b1-47d0-b71b-e961f6c69e56
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1604833768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.1604833768 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_burst_write/latest

Test location	/workspace/coverage/default/30.kmac_entropy_refresh.2939116470
Short name	T550
Test name
Test status
Simulation time	7399199858 ps
CPU time	117.22 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:40:40 PM PDT 24
Peak memory	229832 kb
Host	smart-bb2a9f71-2e0b-42f7-adea-755dd4d4d63f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2939116470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.2939116470 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/30.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/30.kmac_error.3751686781
Short name	T333
Test name
Test status
Simulation time	13188213281 ps
CPU time	353.92 seconds
Started	Jun 13 12:38:41 PM PDT 24
Finished	Jun 13 12:44:36 PM PDT 24
Peak memory	256696 kb
Host	smart-908d52bb-be52-4a14-97d6-b4d3f676ebd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3751686781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3751686781 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_error/latest

Test location	/workspace/coverage/default/30.kmac_key_error.3909870670
Short name	T371
Test name
Test status
Simulation time	1197037649 ps
CPU time	5.9 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 12:38:51 PM PDT 24
Peak memory	215592 kb
Host	smart-2a6cb56b-ab4c-4b7c-b86d-70b0053104d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3909870670 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.3909870670 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_key_error/latest

Test location	/workspace/coverage/default/30.kmac_lc_escalation.3414235137
Short name	T885
Test name
Test status
Simulation time	2633017383 ps
CPU time	12.63 seconds
Started	Jun 13 12:38:41 PM PDT 24
Finished	Jun 13 12:38:54 PM PDT 24
Peak memory	223896 kb
Host	smart-2a34b897-8c2a-456e-bc53-432c67af9ed5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3414235137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.3414235137 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/30.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/30.kmac_long_msg_and_output.1013876613
Short name	T777
Test name
Test status
Simulation time	218102849295 ps
CPU time	1638.13 seconds
Started	Jun 13 12:38:41 PM PDT 24
Finished	Jun 13 01:06:00 PM PDT 24
Peak memory	376224 kb
Host	smart-943c4980-c486-441c-83ad-bbc0a44eca40
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013876613 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a nd_output.1013876613 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/30.kmac_sideload.1333972793
Short name	T352
Test name
Test status
Simulation time	2449157341 ps
CPU time	123.35 seconds
Started	Jun 13 12:38:43 PM PDT 24
Finished	Jun 13 12:40:47 PM PDT 24
Peak memory	230012 kb
Host	smart-dc8afa10-2c0a-4103-8478-af96c5de4417
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333972793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1333972793 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_sideload/latest

Test location	/workspace/coverage/default/30.kmac_smoke.2387589648
Short name	T359
Test name
Test status
Simulation time	818033703 ps
CPU time	43.4 seconds
Started	Jun 13 12:38:40 PM PDT 24
Finished	Jun 13 12:39:24 PM PDT 24
Peak memory	219636 kb
Host	smart-3d652972-3f54-492e-8b46-04046d334ee7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2387589648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.2387589648 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_smoke/latest

Test location	/workspace/coverage/default/30.kmac_stress_all.1082651192
Short name	T844
Test name
Test status
Simulation time	120672370113 ps
CPU time	1249.94 seconds
Started	Jun 13 12:38:46 PM PDT 24
Finished	Jun 13 12:59:37 PM PDT 24
Peak memory	355364 kb
Host	smart-70876363-ac57-4812-95f1-4b245675e255
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1082651192 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.1082651192 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_stress_all/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac.229758245
Short name	T198
Test name
Test status
Simulation time	189668522 ps
CPU time	5.04 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:38:48 PM PDT 24
Peak memory	215780 kb
Host	smart-6bec938f-71da-4baa-a897-3bb040caaa89
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229758245 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 30.kmac_test_vectors_kmac.229758245 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3021479057
Short name	T688
Test name
Test status
Simulation time	74220490 ps
CPU time	4.27 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 12:38:49 PM PDT 24
Peak memory	215704 kb
Host	smart-9128722a-9c0a-4b7c-ace4-22e8f0397eed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021479057 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3021479057 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_224.790136900
Short name	T285
Test name
Test status
Simulation time	74785937647 ps
CPU time	1441.17 seconds
Started	Jun 13 12:38:43 PM PDT 24
Finished	Jun 13 01:02:45 PM PDT 24
Peak memory	366816 kb
Host	smart-dad30831-78ac-4995-8df0-78e0819e1a80
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=790136900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.790136900 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_256.991058342
Short name	T982
Test name
Test status
Simulation time	169504917577 ps
CPU time	1791.85 seconds
Started	Jun 13 12:38:43 PM PDT 24
Finished	Jun 13 01:08:36 PM PDT 24
Peak memory	367924 kb
Host	smart-b4fc2391-b4c0-4a48-bd7e-e02c97993de0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=991058342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.991058342 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_384.1921473111
Short name	T341
Test name
Test status
Simulation time	574856984528 ps
CPU time	1382.91 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 01:01:48 PM PDT 24
Peak memory	330632 kb
Host	smart-30542f42-687a-486f-8671-332910c7beec
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1921473111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.1921473111 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_sha3_512.3505384793
Short name	T621
Test name
Test status
Simulation time	130889452970 ps
CPU time	856.47 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:52:59 PM PDT 24
Peak memory	294932 kb
Host	smart-7308f410-f970-4d62-a0d8-cd8f8b1589e4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3505384793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.3505384793 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_128.1821266912
Short name	T836
Test name
Test status
Simulation time	230954213542 ps
CPU time	3833.13 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 01:42:39 PM PDT 24
Peak memory	649080 kb
Host	smart-1a2fb5c5-80d9-4fcc-bb02-2a1877208a6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1821266912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.1821266912 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/30.kmac_test_vectors_shake_256.3196354596
Short name	T112
Test name
Test status
Simulation time	44424730081 ps
CPU time	3484 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 01:36:47 PM PDT 24
Peak memory	549856 kb
Host	smart-8cc36b6a-3e4a-4ee0-8157-6034c64329cf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3196354596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.3196354596 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/30.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/31.kmac_alert_test.3525973092
Short name	T19
Test name
Test status
Simulation time	16804187 ps
CPU time	0.8 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 12:38:52 PM PDT 24
Peak memory	205240 kb
Host	smart-0e4f36eb-54b6-4ced-9e61-acacfc5612c5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525973092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.3525973092 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_alert_test/latest

Test location	/workspace/coverage/default/31.kmac_app.3878597548
Short name	T908
Test name
Test status
Simulation time	5975818501 ps
CPU time	142.39 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 12:41:09 PM PDT 24
Peak memory	233744 kb
Host	smart-be346f57-7d00-4dc2-b9b4-fa450a0885d7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3878597548 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.3878597548 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_app/latest

Test location	/workspace/coverage/default/31.kmac_burst_write.1200135930
Short name	T502
Test name
Test status
Simulation time	63317308000 ps
CPU time	491.14 seconds
Started	Jun 13 12:38:49 PM PDT 24
Finished	Jun 13 12:47:01 PM PDT 24
Peak memory	229376 kb
Host	smart-5dcb4e43-9371-4854-9146-40ac08136785
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200135930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.1200135930 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_burst_write/latest

Test location	/workspace/coverage/default/31.kmac_entropy_refresh.3355064289
Short name	T575
Test name
Test status
Simulation time	8013888095 ps
CPU time	220.41 seconds
Started	Jun 13 12:38:49 PM PDT 24
Finished	Jun 13 12:42:30 PM PDT 24
Peak memory	244224 kb
Host	smart-e1549441-eb0a-40d9-a15b-9945841c4477
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3355064289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3355064289 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/31.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/31.kmac_error.1920070826
Short name	T810
Test name
Test status
Simulation time	11542304822 ps
CPU time	294.09 seconds
Started	Jun 13 12:38:43 PM PDT 24
Finished	Jun 13 12:43:38 PM PDT 24
Peak memory	254500 kb
Host	smart-d20253da-f940-4cd0-88ba-34c7fc262354
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1920070826 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1920070826 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_error/latest

Test location	/workspace/coverage/default/31.kmac_key_error.3834820489
Short name	T486
Test name
Test status
Simulation time	533380084 ps
CPU time	1.95 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 12:38:46 PM PDT 24
Peak memory	215648 kb
Host	smart-ffa80636-709f-4661-908b-7b0fb4fb9050
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3834820489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.3834820489 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_key_error/latest

Test location	/workspace/coverage/default/31.kmac_lc_escalation.2056281016
Short name	T6
Test name
Test status
Simulation time	503720636 ps
CPU time	18.54 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:39:02 PM PDT 24
Peak memory	225108 kb
Host	smart-9c6cac2c-9687-4c7a-9dad-e006e83d2040
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2056281016 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2056281016 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/31.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/31.kmac_long_msg_and_output.3759790376
Short name	T622
Test name
Test status
Simulation time	59003122766 ps
CPU time	1688.13 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 01:06:53 PM PDT 24
Peak memory	390968 kb
Host	smart-6f2f2da3-0a79-465a-b581-723edd7ca274
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759790376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a nd_output.3759790376 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/31.kmac_sideload.3988065551
Short name	T831
Test name
Test status
Simulation time	26991776451 ps
CPU time	278.64 seconds
Started	Jun 13 12:38:47 PM PDT 24
Finished	Jun 13 12:43:26 PM PDT 24
Peak memory	239984 kb
Host	smart-daa1586c-a94b-4b2d-814c-2ccfba600b52
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988065551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.3988065551 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_sideload/latest

Test location	/workspace/coverage/default/31.kmac_smoke.3417759125
Short name	T363
Test name
Test status
Simulation time	4355119018 ps
CPU time	42.22 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 12:39:27 PM PDT 24
Peak memory	219380 kb
Host	smart-bb139646-fbaa-4a5d-b941-f89ede06d5c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417759125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.3417759125 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_smoke/latest

Test location	/workspace/coverage/default/31.kmac_stress_all.2124123860
Short name	T72
Test name
Test status
Simulation time	225099578218 ps
CPU time	2453.38 seconds
Started	Jun 13 12:38:47 PM PDT 24
Finished	Jun 13 01:19:41 PM PDT 24
Peak memory	464864 kb
Host	smart-6bd5f2d7-6c6c-4b50-8923-27964dd362b0
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2124123860 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.2124123860 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all/latest

Test location	/workspace/coverage/default/31.kmac_stress_all_with_rand_reset.3193584737
Short name	T106
Test name
Test status
Simulation time	19460848061 ps
CPU time	493.33 seconds
Started	Jun 13 12:38:47 PM PDT 24
Finished	Jun 13 12:47:01 PM PDT 24
Peak memory	265376 kb
Host	smart-b16231ab-4c61-43a3-b6e7-e03f7d205c3a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3193584737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all_with_rand_reset.3193584737 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac.3079732504
Short name	T718
Test name
Test status
Simulation time	608371928 ps
CPU time	5.01 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 12:38:49 PM PDT 24
Peak memory	215768 kb
Host	smart-223a0360-f55b-4122-93be-a6233a432baa
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079732504 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 31.kmac_test_vectors_kmac.3079732504 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_kmac_xof.1297183632
Short name	T444
Test name
Test status
Simulation time	1221927771 ps
CPU time	5.11 seconds
Started	Jun 13 12:38:46 PM PDT 24
Finished	Jun 13 12:38:52 PM PDT 24
Peak memory	215860 kb
Host	smart-8ec98ab5-13b4-43fa-81af-958a30135ef4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297183632 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_kmac_xof.1297183632 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_224.1218186513
Short name	T760
Test name
Test status
Simulation time	18588001816 ps
CPU time	1471.48 seconds
Started	Jun 13 12:38:45 PM PDT 24
Finished	Jun 13 01:03:17 PM PDT 24
Peak memory	387384 kb
Host	smart-6b64b2a2-105a-4283-8f9d-b6cb5a01084a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1218186513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.1218186513 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_256.1506952821
Short name	T258
Test name
Test status
Simulation time	70924714627 ps
CPU time	1312.31 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 01:00:37 PM PDT 24
Peak memory	374792 kb
Host	smart-e16f988f-c1b2-4863-9410-8633d69962ef
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1506952821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.1506952821 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_384.1327600222
Short name	T213
Test name
Test status
Simulation time	146049851258 ps
CPU time	1508.62 seconds
Started	Jun 13 12:38:42 PM PDT 24
Finished	Jun 13 01:03:51 PM PDT 24
Peak memory	334632 kb
Host	smart-73f02904-d886-4f17-85cd-375937877a93
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1327600222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.1327600222 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_sha3_512.2085538650
Short name	T12
Test name
Test status
Simulation time	87752078130 ps
CPU time	857.86 seconds
Started	Jun 13 12:38:46 PM PDT 24
Finished	Jun 13 12:53:05 PM PDT 24
Peak memory	294108 kb
Host	smart-f1e9fdb9-5641-4e46-8ef8-0b10fe6b7c26
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2085538650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.2085538650 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_128.410870
Short name	T430
Test name
Test status
Simulation time	180859222217 ps
CPU time	4799.21 seconds
Started	Jun 13 12:38:47 PM PDT 24
Finished	Jun 13 01:58:47 PM PDT 24
Peak memory	659920 kb
Host	smart-2205db9d-a5af-44b9-9827-b1dd391d8557
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=410870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.410870 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/31.kmac_test_vectors_shake_256.3269145640
Short name	T1054
Test name
Test status
Simulation time	43535503300 ps
CPU time	3289.59 seconds
Started	Jun 13 12:38:44 PM PDT 24
Finished	Jun 13 01:33:35 PM PDT 24
Peak memory	566368 kb
Host	smart-4341d13c-1ce5-4eac-8cf4-f6d4e43e2e0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3269145640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.3269145640 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/31.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/32.kmac_alert_test.1630905793
Short name	T816
Test name
Test status
Simulation time	48694858 ps
CPU time	0.81 seconds
Started	Jun 13 12:38:53 PM PDT 24
Finished	Jun 13 12:38:54 PM PDT 24
Peak memory	205108 kb
Host	smart-432bdee2-6cb6-442e-85e3-7f14769c2354
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630905793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.1630905793 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_alert_test/latest

Test location	/workspace/coverage/default/32.kmac_app.2205884929
Short name	T1089
Test name
Test status
Simulation time	11478973919 ps
CPU time	175.06 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 12:41:47 PM PDT 24
Peak memory	238092 kb
Host	smart-67bfd7b8-42c4-4e93-87f5-4f4424044009
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2205884929 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.2205884929 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_app/latest

Test location	/workspace/coverage/default/32.kmac_entropy_refresh.4161672163
Short name	T468
Test name
Test status
Simulation time	51742341359 ps
CPU time	233.3 seconds
Started	Jun 13 12:38:53 PM PDT 24
Finished	Jun 13 12:42:47 PM PDT 24
Peak memory	240516 kb
Host	smart-04c15c49-1236-4482-808d-253c00e1a51e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4161672163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.4161672163 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/32.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/32.kmac_error.828972912
Short name	T23
Test name
Test status
Simulation time	1206975916 ps
CPU time	97.15 seconds
Started	Jun 13 12:38:54 PM PDT 24
Finished	Jun 13 12:40:32 PM PDT 24
Peak memory	240372 kb
Host	smart-949a3e50-f6fe-49d5-8ab4-fb9d3682eea0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=828972912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.828972912 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_error/latest

Test location	/workspace/coverage/default/32.kmac_key_error.1774667463
Short name	T742
Test name
Test status
Simulation time	7166658264 ps
CPU time	8.01 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 12:39:00 PM PDT 24
Peak memory	207508 kb
Host	smart-39b19755-7f38-4b60-bcf2-231c2c43b7c6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774667463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1774667463 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_key_error/latest

Test location	/workspace/coverage/default/32.kmac_lc_escalation.915106468
Short name	T749
Test name
Test status
Simulation time	111212867 ps
CPU time	1.31 seconds
Started	Jun 13 12:38:54 PM PDT 24
Finished	Jun 13 12:38:56 PM PDT 24
Peak memory	215652 kb
Host	smart-08b97802-9f8a-4edf-9c33-3bca3fddc433
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915106468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.915106468 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/32.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/32.kmac_long_msg_and_output.3671062678
Short name	T331
Test name
Test status
Simulation time	40860943040 ps
CPU time	895.19 seconds
Started	Jun 13 12:38:52 PM PDT 24
Finished	Jun 13 12:53:48 PM PDT 24
Peak memory	316008 kb
Host	smart-3722013c-05e2-435b-890e-bbb84a64941d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671062678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a nd_output.3671062678 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/32.kmac_sideload.1393814330
Short name	T966
Test name
Test status
Simulation time	73301102341 ps
CPU time	406.31 seconds
Started	Jun 13 12:38:54 PM PDT 24
Finished	Jun 13 12:45:41 PM PDT 24
Peak memory	248092 kb
Host	smart-935c908c-b8f1-408c-9c92-19a2035abfc0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393814330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.1393814330 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_sideload/latest

Test location	/workspace/coverage/default/32.kmac_smoke.1888250541
Short name	T769
Test name
Test status
Simulation time	6322242302 ps
CPU time	25.72 seconds
Started	Jun 13 12:38:52 PM PDT 24
Finished	Jun 13 12:39:18 PM PDT 24
Peak memory	219316 kb
Host	smart-32eaf3fe-c3f4-4122-a4d6-b34b94d18c05
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888250541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.1888250541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_smoke/latest

Test location	/workspace/coverage/default/32.kmac_stress_all.2995229791
Short name	T493
Test name
Test status
Simulation time	46912289711 ps
CPU time	340.74 seconds
Started	Jun 13 12:38:56 PM PDT 24
Finished	Jun 13 12:44:37 PM PDT 24
Peak memory	248672 kb
Host	smart-7197f7eb-34c2-44c1-8156-9e67023129bc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2995229791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.2995229791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_stress_all/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac.499680456
Short name	T566
Test name
Test status
Simulation time	676991267 ps
CPU time	4.12 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 12:38:55 PM PDT 24
Peak memory	215776 kb
Host	smart-0e2458b4-65cf-4a5a-a7af-86217f51d5c6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499680456 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 32.kmac_test_vectors_kmac.499680456 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_kmac_xof.138775949
Short name	T723
Test name
Test status
Simulation time	260464314 ps
CPU time	4.41 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 12:38:56 PM PDT 24
Peak memory	215676 kb
Host	smart-c00d64cf-e994-4952-8aa8-de517c64ca34
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138775949 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 32.kmac_test_vectors_kmac_xof.138775949 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_224.627697569
Short name	T94
Test name
Test status
Simulation time	102941200234 ps
CPU time	1432.43 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 01:02:44 PM PDT 24
Peak memory	378804 kb
Host	smart-9b71326d-bdda-4362-800f-5c7cadaeb87a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=627697569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.627697569 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_256.2368881497
Short name	T446
Test name
Test status
Simulation time	279657417409 ps
CPU time	1779.86 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 01:08:32 PM PDT 24
Peak memory	377200 kb
Host	smart-b30f78b4-a0d4-4957-a26f-17f9fe754716
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2368881497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.2368881497 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_384.1251028703
Short name	T569
Test name
Test status
Simulation time	188753406413 ps
CPU time	1313.32 seconds
Started	Jun 13 12:38:52 PM PDT 24
Finished	Jun 13 01:00:47 PM PDT 24
Peak memory	336368 kb
Host	smart-fa68e832-dbbe-4dd6-95d3-30dac004f3c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1251028703 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.1251028703 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_sha3_512.337829366
Short name	T904
Test name
Test status
Simulation time	67865816714 ps
CPU time	829.68 seconds
Started	Jun 13 12:38:52 PM PDT 24
Finished	Jun 13 12:52:43 PM PDT 24
Peak memory	298584 kb
Host	smart-2feb7d00-befa-48a5-94ed-e019a6540fe4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=337829366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.337829366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_128.3658052208
Short name	T361
Test name
Test status
Simulation time	167548339888 ps
CPU time	4468.42 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 01:53:21 PM PDT 24
Peak memory	626904 kb
Host	smart-415a6fe1-1f8d-4a90-92ed-076257dde57b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3658052208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3658052208 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/32.kmac_test_vectors_shake_256.2142439956
Short name	T159
Test name
Test status
Simulation time	145326066086 ps
CPU time	3655.52 seconds
Started	Jun 13 12:38:51 PM PDT 24
Finished	Jun 13 01:39:47 PM PDT 24
Peak memory	561140 kb
Host	smart-db8aaf3d-c651-49de-a52a-f71b47126e45
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2142439956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.2142439956 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/32.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/33.kmac_alert_test.2199493913
Short name	T755
Test name
Test status
Simulation time	95850230 ps
CPU time	0.75 seconds
Started	Jun 13 12:38:57 PM PDT 24
Finished	Jun 13 12:38:58 PM PDT 24
Peak memory	205228 kb
Host	smart-c2c2083f-1da9-4740-8a0c-a8dae52c7506
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199493913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2199493913 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_alert_test/latest

Test location	/workspace/coverage/default/33.kmac_app.1481827559
Short name	T42
Test name
Test status
Simulation time	80544959038 ps
CPU time	301.02 seconds
Started	Jun 13 12:39:00 PM PDT 24
Finished	Jun 13 12:44:02 PM PDT 24
Peak memory	242352 kb
Host	smart-e4796fe4-9f32-40b8-9df2-87d8dbba5bf9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1481827559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.1481827559 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_app/latest

Test location	/workspace/coverage/default/33.kmac_burst_write.1249437958
Short name	T119
Test name
Test status
Simulation time	22378334494 ps
CPU time	617.71 seconds
Started	Jun 13 12:38:56 PM PDT 24
Finished	Jun 13 12:49:14 PM PDT 24
Peak memory	236284 kb
Host	smart-0a1e075f-a723-4457-bbf4-c65e448f6319
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249437958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1249437958 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_burst_write/latest

Test location	/workspace/coverage/default/33.kmac_entropy_refresh.3719649441
Short name	T490
Test name
Test status
Simulation time	6365176243 ps
CPU time	202.67 seconds
Started	Jun 13 12:39:01 PM PDT 24
Finished	Jun 13 12:42:24 PM PDT 24
Peak memory	239944 kb
Host	smart-17474614-75e0-4ef3-a646-97372be7c013
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3719649441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3719649441 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/33.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/33.kmac_error.3288603326
Short name	T382
Test name
Test status
Simulation time	3261386085 ps
CPU time	236.76 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 12:42:56 PM PDT 24
Peak memory	256712 kb
Host	smart-e9059ee9-70cf-4f19-8683-8e4dc726fdc1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3288603326 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.3288603326 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_error/latest

Test location	/workspace/coverage/default/33.kmac_key_error.2774985455
Short name	T338
Test name
Test status
Simulation time	840477365 ps
CPU time	4.1 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 12:39:04 PM PDT 24
Peak memory	215696 kb
Host	smart-e66ef8cf-93eb-48a5-b7e2-86870a083159
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774985455 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.2774985455 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_key_error/latest

Test location	/workspace/coverage/default/33.kmac_lc_escalation.1945284824
Short name	T530
Test name
Test status
Simulation time	46861180 ps
CPU time	1.33 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 12:38:59 PM PDT 24
Peak memory	215704 kb
Host	smart-762df933-9625-43c1-bdb0-f3cb11475166
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1945284824 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1945284824 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/33.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/33.kmac_long_msg_and_output.2598514182
Short name	T167
Test name
Test status
Simulation time	132552888766 ps
CPU time	956.67 seconds
Started	Jun 13 12:38:53 PM PDT 24
Finished	Jun 13 12:54:51 PM PDT 24
Peak memory	310340 kb
Host	smart-a887c044-de37-4a1f-9979-3228da83cc16
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598514182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a nd_output.2598514182 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/33.kmac_sideload.3067874273
Short name	T978
Test name
Test status
Simulation time	24677561218 ps
CPU time	138.61 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 12:41:18 PM PDT 24
Peak memory	229264 kb
Host	smart-976d7b60-1460-4299-996a-9b90e3c77f97
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067874273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.3067874273 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_sideload/latest

Test location	/workspace/coverage/default/33.kmac_smoke.3490999228
Short name	T110
Test name
Test status
Simulation time	1573387976 ps
CPU time	20.26 seconds
Started	Jun 13 12:38:53 PM PDT 24
Finished	Jun 13 12:39:14 PM PDT 24
Peak memory	217460 kb
Host	smart-1597bb00-663f-4c67-ac77-f405efa94f14
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3490999228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3490999228 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_smoke/latest

Test location	/workspace/coverage/default/33.kmac_stress_all.2691113074
Short name	T898
Test name
Test status
Simulation time	22191595294 ps
CPU time	470.9 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 12:46:49 PM PDT 24
Peak memory	305152 kb
Host	smart-1371d0c4-2f0e-472f-98f6-2d197aeb513f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2691113074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.2691113074 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_stress_all/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac.1827778015
Short name	T984
Test name
Test status
Simulation time	175037264 ps
CPU time	5.3 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 12:39:04 PM PDT 24
Peak memory	209324 kb
Host	smart-e22de89a-a2dc-4d41-ad17-296f92928da3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827778015 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 33.kmac_test_vectors_kmac.1827778015 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_kmac_xof.365132526
Short name	T1081
Test name
Test status
Simulation time	252301221 ps
CPU time	4.34 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 12:39:04 PM PDT 24
Peak memory	215848 kb
Host	smart-970f02dd-0043-4d6a-b47c-c2a3c63558e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365132526 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 33.kmac_test_vectors_kmac_xof.365132526 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_224.1565702154
Short name	T210
Test name
Test status
Simulation time	101590618499 ps
CPU time	1978.62 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 01:11:57 PM PDT 24
Peak memory	393596 kb
Host	smart-ef755dda-48f3-490c-b19f-0d7aa9adf32c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1565702154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1565702154 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_256.2428844445
Short name	T504
Test name
Test status
Simulation time	89226048620 ps
CPU time	1721.53 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 01:07:41 PM PDT 24
Peak memory	362096 kb
Host	smart-b5c25d13-1d53-4101-b80d-7b9abeb98f0e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2428844445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.2428844445 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_384.3660628208
Short name	T1046
Test name
Test status
Simulation time	47582762358 ps
CPU time	1193.9 seconds
Started	Jun 13 12:38:56 PM PDT 24
Finished	Jun 13 12:58:50 PM PDT 24
Peak memory	327172 kb
Host	smart-d0a002ab-c9c1-4378-a56d-44d0e7f6e0c7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3660628208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3660628208 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_sha3_512.4005350134
Short name	T574
Test name
Test status
Simulation time	107247772531 ps
CPU time	818.51 seconds
Started	Jun 13 12:38:57 PM PDT 24
Finished	Jun 13 12:52:36 PM PDT 24
Peak memory	297840 kb
Host	smart-c508bcc0-5862-4fc3-bbe9-7b75d9e11513
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4005350134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.4005350134 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_128.3900749928
Short name	T772
Test name
Test status
Simulation time	52103003073 ps
CPU time	3847.19 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 01:43:07 PM PDT 24
Peak memory	643612 kb
Host	smart-043861e3-5d2c-478b-a98a-3c0cb326a146
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3900749928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.3900749928 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/33.kmac_test_vectors_shake_256.1939306801
Short name	T827
Test name
Test status
Simulation time	165757158028 ps
CPU time	3783.25 seconds
Started	Jun 13 12:39:02 PM PDT 24
Finished	Jun 13 01:42:06 PM PDT 24
Peak memory	564152 kb
Host	smart-c361f855-0dfb-47ed-b275-013943fc1eb8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1939306801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1939306801 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/33.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/34.kmac_alert_test.3276097569
Short name	T692
Test name
Test status
Simulation time	16537536 ps
CPU time	0.81 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 12:39:18 PM PDT 24
Peak memory	205208 kb
Host	smart-8588e51c-cf30-4045-8c6c-beeca3e57fcc
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276097569 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.3276097569 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_alert_test/latest

Test location	/workspace/coverage/default/34.kmac_app.3829882777
Short name	T172
Test name
Test status
Simulation time	5181434474 ps
CPU time	67.93 seconds
Started	Jun 13 12:39:03 PM PDT 24
Finished	Jun 13 12:40:11 PM PDT 24
Peak memory	225812 kb
Host	smart-0263ba53-f02b-46cd-8c02-be7d6088ee9a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3829882777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.3829882777 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_app/latest

Test location	/workspace/coverage/default/34.kmac_burst_write.439436807
Short name	T938
Test name
Test status
Simulation time	21007611199 ps
CPU time	254.83 seconds
Started	Jun 13 12:39:02 PM PDT 24
Finished	Jun 13 12:43:17 PM PDT 24
Peak memory	225028 kb
Host	smart-79926dda-db72-412c-99f4-4037e366ceb3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=439436807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.439436807 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_burst_write/latest

Test location	/workspace/coverage/default/34.kmac_entropy_refresh.2024605608
Short name	T1076
Test name
Test status
Simulation time	26564989237 ps
CPU time	127.48 seconds
Started	Jun 13 12:39:04 PM PDT 24
Finished	Jun 13 12:41:12 PM PDT 24
Peak memory	233288 kb
Host	smart-df9ef2ba-0fec-44d9-8ea5-912979537faf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2024605608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2024605608 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/34.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/34.kmac_error.1991603817
Short name	T336
Test name
Test status
Simulation time	54424618228 ps
CPU time	220.03 seconds
Started	Jun 13 12:39:04 PM PDT 24
Finished	Jun 13 12:42:45 PM PDT 24
Peak memory	248660 kb
Host	smart-3638e21e-7286-478a-a331-53f204343548
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1991603817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.1991603817 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_error/latest

Test location	/workspace/coverage/default/34.kmac_key_error.3093159651
Short name	T59
Test name
Test status
Simulation time	7066148515 ps
CPU time	10.14 seconds
Started	Jun 13 12:39:03 PM PDT 24
Finished	Jun 13 12:39:14 PM PDT 24
Peak memory	207480 kb
Host	smart-cb59a325-5cb7-4e34-a0c7-18f23aed8b8e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093159651 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.3093159651 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_key_error/latest

Test location	/workspace/coverage/default/34.kmac_long_msg_and_output.477583001
Short name	T587
Test name
Test status
Simulation time	105426894230 ps
CPU time	768.85 seconds
Started	Jun 13 12:38:57 PM PDT 24
Finished	Jun 13 12:51:47 PM PDT 24
Peak memory	294664 kb
Host	smart-24983193-6f05-4708-93e5-7b2f3c916113
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477583001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an d_output.477583001 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/34.kmac_sideload.3374476256
Short name	T227
Test name
Test status
Simulation time	31395417047 ps
CPU time	343.52 seconds
Started	Jun 13 12:38:58 PM PDT 24
Finished	Jun 13 12:44:42 PM PDT 24
Peak memory	242912 kb
Host	smart-00fa762b-d684-46bd-9156-50f33667e606
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374476256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.3374476256 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_sideload/latest

Test location	/workspace/coverage/default/34.kmac_smoke.1762940301
Short name	T986
Test name
Test status
Simulation time	2253839782 ps
CPU time	44.76 seconds
Started	Jun 13 12:39:01 PM PDT 24
Finished	Jun 13 12:39:46 PM PDT 24
Peak memory	215992 kb
Host	smart-eccc6705-778e-43b0-ab45-55b71a41acec
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1762940301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.1762940301 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_smoke/latest

Test location	/workspace/coverage/default/34.kmac_stress_all.3424133250
Short name	T1033
Test name
Test status
Simulation time	3839580268 ps
CPU time	101.29 seconds
Started	Jun 13 12:39:03 PM PDT 24
Finished	Jun 13 12:40:45 PM PDT 24
Peak memory	240472 kb
Host	smart-9b63614a-4ab4-448d-8362-a0492d1150cc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3424133250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.3424133250 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_stress_all/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac.2103244778
Short name	T1074
Test name
Test status
Simulation time	72860056 ps
CPU time	4.3 seconds
Started	Jun 13 12:39:03 PM PDT 24
Finished	Jun 13 12:39:08 PM PDT 24
Peak memory	215984 kb
Host	smart-a81c1929-75d6-4b56-b9f9-14271103516d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103244778 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 34.kmac_test_vectors_kmac.2103244778 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_kmac_xof.2719425203
Short name	T180
Test name
Test status
Simulation time	491906926 ps
CPU time	5.37 seconds
Started	Jun 13 12:39:04 PM PDT 24
Finished	Jun 13 12:39:10 PM PDT 24
Peak memory	208944 kb
Host	smart-7252fa6c-a87e-4ab9-b471-eb0529481848
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719425203 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_kmac_xof.2719425203 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_224.4234856017
Short name	T940
Test name
Test status
Simulation time	67412771927 ps
CPU time	1717.06 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 01:07:37 PM PDT 24
Peak memory	395148 kb
Host	smart-a244d9bd-9192-4208-8fc1-15b676575a33
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4234856017 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.4234856017 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_256.2853856099
Short name	T470
Test name
Test status
Simulation time	403187110521 ps
CPU time	1636.99 seconds
Started	Jun 13 12:38:59 PM PDT 24
Finished	Jun 13 01:06:17 PM PDT 24
Peak memory	371080 kb
Host	smart-a6036d30-50e2-4226-8ae4-c15e7906b394
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2853856099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.2853856099 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_384.3872512864
Short name	T717
Test name
Test status
Simulation time	13449067293 ps
CPU time	1081.08 seconds
Started	Jun 13 12:39:00 PM PDT 24
Finished	Jun 13 12:57:01 PM PDT 24
Peak memory	331924 kb
Host	smart-3be9dfff-8ea2-4d71-8141-582f93c3b57a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3872512864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.3872512864 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_sha3_512.1068595506
Short name	T702
Test name
Test status
Simulation time	14219100523 ps
CPU time	820.79 seconds
Started	Jun 13 12:39:02 PM PDT 24
Finished	Jun 13 12:52:43 PM PDT 24
Peak memory	295076 kb
Host	smart-847ff6f1-aabe-459f-bcc4-a95bb6296e95
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1068595506 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1068595506 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_128.3890202052
Short name	T271
Test name
Test status
Simulation time	343050246763 ps
CPU time	4667.38 seconds
Started	Jun 13 12:39:01 PM PDT 24
Finished	Jun 13 01:56:50 PM PDT 24
Peak memory	627960 kb
Host	smart-bb8b9dbb-cfc0-47cb-bdcb-c1307b2ce0f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3890202052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.3890202052 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/34.kmac_test_vectors_shake_256.2679053933
Short name	T370
Test name
Test status
Simulation time	215905811911 ps
CPU time	4015.77 seconds
Started	Jun 13 12:39:03 PM PDT 24
Finished	Jun 13 01:45:59 PM PDT 24
Peak memory	557956 kb
Host	smart-eabfe78c-a3b1-4510-b826-e73a24dae788
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2679053933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.2679053933 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/34.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/35.kmac_alert_test.3239256634
Short name	T924
Test name
Test status
Simulation time	47046735 ps
CPU time	0.75 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 12:39:18 PM PDT 24
Peak memory	205252 kb
Host	smart-b6857b6f-f210-4d8c-b0a5-3ab23fb5718d
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239256634 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3239256634 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_alert_test/latest

Test location	/workspace/coverage/default/35.kmac_app.3334098944
Short name	T356
Test name
Test status
Simulation time	8885936623 ps
CPU time	116.94 seconds
Started	Jun 13 12:39:18 PM PDT 24
Finished	Jun 13 12:41:16 PM PDT 24
Peak memory	230720 kb
Host	smart-7481f62a-0836-49cb-8987-268a1a63b30a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3334098944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.3334098944 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_app/latest

Test location	/workspace/coverage/default/35.kmac_burst_write.888103883
Short name	T232
Test name
Test status
Simulation time	4308765428 ps
CPU time	27.92 seconds
Started	Jun 13 12:39:15 PM PDT 24
Finished	Jun 13 12:39:44 PM PDT 24
Peak memory	217628 kb
Host	smart-36794089-c418-43c0-90fe-ae4e62a176d2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=888103883 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.888103883 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_burst_write/latest

Test location	/workspace/coverage/default/35.kmac_entropy_refresh.1048310656
Short name	T838
Test name
Test status
Simulation time	2291729494 ps
CPU time	36.5 seconds
Started	Jun 13 12:39:21 PM PDT 24
Finished	Jun 13 12:39:59 PM PDT 24
Peak memory	221012 kb
Host	smart-de66725c-219e-4493-9ae0-1e2df2fe45a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1048310656 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1048310656 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/35.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/35.kmac_error.3171246376
Short name	T668
Test name
Test status
Simulation time	2798977022 ps
CPU time	205.03 seconds
Started	Jun 13 12:39:19 PM PDT 24
Finished	Jun 13 12:42:45 PM PDT 24
Peak memory	253976 kb
Host	smart-c16826bf-a53d-4506-9095-b4af657994a9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171246376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.3171246376 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_error/latest

Test location	/workspace/coverage/default/35.kmac_key_error.855914239
Short name	T58
Test name
Test status
Simulation time	326297280 ps
CPU time	2.78 seconds
Started	Jun 13 12:39:20 PM PDT 24
Finished	Jun 13 12:39:23 PM PDT 24
Peak memory	207312 kb
Host	smart-a32eef3b-bb3a-41c9-8ca6-f90b87c70739
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=855914239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.855914239 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_key_error/latest

Test location	/workspace/coverage/default/35.kmac_lc_escalation.1021831647
Short name	T439
Test name
Test status
Simulation time	55648876 ps
CPU time	1.16 seconds
Started	Jun 13 12:39:20 PM PDT 24
Finished	Jun 13 12:39:21 PM PDT 24
Peak memory	215516 kb
Host	smart-38919027-0411-44e7-8b1e-9522671153b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021831647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.1021831647 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/35.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/35.kmac_long_msg_and_output.1998635515
Short name	T201
Test name
Test status
Simulation time	5177839360 ps
CPU time	454.52 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 12:46:52 PM PDT 24
Peak memory	266996 kb
Host	smart-f0b0439d-4001-479e-8b17-dbc1c77fde90
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998635515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a nd_output.1998635515 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/35.kmac_sideload.2815111821
Short name	T848
Test name
Test status
Simulation time	4529761619 ps
CPU time	346.65 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 12:45:04 PM PDT 24
Peak memory	248232 kb
Host	smart-ae5680ae-c028-4f81-9740-0fa5a328b5d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815111821 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.2815111821 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_sideload/latest

Test location	/workspace/coverage/default/35.kmac_smoke.1976637341
Short name	T695
Test name
Test status
Simulation time	3184566989 ps
CPU time	39.81 seconds
Started	Jun 13 12:39:21 PM PDT 24
Finished	Jun 13 12:40:02 PM PDT 24
Peak memory	215836 kb
Host	smart-af985516-0bc7-446b-baf7-a8b344473b92
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1976637341 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.1976637341 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_smoke/latest

Test location	/workspace/coverage/default/35.kmac_stress_all.3674812787
Short name	T74
Test name
Test status
Simulation time	48967248702 ps
CPU time	466.19 seconds
Started	Jun 13 12:39:27 PM PDT 24
Finished	Jun 13 12:47:14 PM PDT 24
Peak memory	298792 kb
Host	smart-3702d826-4aee-4b1d-8280-555af9dead23
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3674812787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3674812787 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_stress_all/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac.3951824792
Short name	T737
Test name
Test status
Simulation time	1245965192 ps
CPU time	4.74 seconds
Started	Jun 13 12:39:20 PM PDT 24
Finished	Jun 13 12:39:25 PM PDT 24
Peak memory	215780 kb
Host	smart-86f008f8-a1ef-4b2b-92da-e4f6668f0bd2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951824792 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 35.kmac_test_vectors_kmac.3951824792 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2940292399
Short name	T881
Test name
Test status
Simulation time	693177911 ps
CPU time	5.1 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:39:23 PM PDT 24
Peak memory	215800 kb
Host	smart-aea0b3ed-fea5-4eb1-b045-eb7ab646df0c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940292399 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2940292399 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_224.502840509
Short name	T869
Test name
Test status
Simulation time	362766810168 ps
CPU time	1717.7 seconds
Started	Jun 13 12:39:18 PM PDT 24
Finished	Jun 13 01:07:57 PM PDT 24
Peak memory	395108 kb
Host	smart-32f649b0-dc70-42db-b7c6-1ef677bd9222
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=502840509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.502840509 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_256.3099104179
Short name	T235
Test name
Test status
Simulation time	35835341128 ps
CPU time	1432.55 seconds
Started	Jun 13 12:39:18 PM PDT 24
Finished	Jun 13 01:03:12 PM PDT 24
Peak memory	363348 kb
Host	smart-a6af45e8-98a9-4f44-8db4-02eaf17f2bbe
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3099104179 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.3099104179 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_384.1231669575
Short name	T576
Test name
Test status
Simulation time	62643820941 ps
CPU time	1341.32 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 01:01:40 PM PDT 24
Peak memory	334740 kb
Host	smart-e0b4dd55-1e43-498b-bf1f-9cbeaec2ac12
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1231669575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1231669575 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_sha3_512.3296826709
Short name	T942
Test name
Test status
Simulation time	32743619464 ps
CPU time	756.22 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:51:55 PM PDT 24
Peak memory	294760 kb
Host	smart-15337e38-4245-49e3-aa59-8bb2e934026b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3296826709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.3296826709 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_128.1429652688
Short name	T369
Test name
Test status
Simulation time	180166114178 ps
CPU time	4872.04 seconds
Started	Jun 13 12:39:19 PM PDT 24
Finished	Jun 13 02:00:33 PM PDT 24
Peak memory	655340 kb
Host	smart-55ca12c4-3a79-4fb0-beaf-92f07d7bd51b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1429652688 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.1429652688 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/35.kmac_test_vectors_shake_256.2860720323
Short name	T812
Test name
Test status
Simulation time	151173167797 ps
CPU time	3933.18 seconds
Started	Jun 13 12:39:21 PM PDT 24
Finished	Jun 13 01:44:56 PM PDT 24
Peak memory	568612 kb
Host	smart-fc655c33-732d-48d5-a4f4-2ace90370640
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2860720323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.2860720323 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/35.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/36.kmac_alert_test.1823998795
Short name	T683
Test name
Test status
Simulation time	22655100 ps
CPU time	0.86 seconds
Started	Jun 13 12:39:23 PM PDT 24
Finished	Jun 13 12:39:25 PM PDT 24
Peak memory	205252 kb
Host	smart-cfe0eb4c-d56e-46aa-9bbd-3c20c09a4668
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823998795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.1823998795 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_alert_test/latest

Test location	/workspace/coverage/default/36.kmac_app.2554455471
Short name	T375
Test name
Test status
Simulation time	9413810258 ps
CPU time	44.58 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:40:03 PM PDT 24
Peak memory	224004 kb
Host	smart-5a1c0627-256e-4915-a8e0-db5b4e6d4dc3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554455471 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.2554455471 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_app/latest

Test location	/workspace/coverage/default/36.kmac_burst_write.3607580714
Short name	T422
Test name
Test status
Simulation time	124612367164 ps
CPU time	835.98 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:53:15 PM PDT 24
Peak memory	232544 kb
Host	smart-ae02fe88-bd65-4d00-a6e9-97538637e4ae
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3607580714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3607580714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_burst_write/latest

Test location	/workspace/coverage/default/36.kmac_entropy_refresh.890829188
Short name	T520
Test name
Test status
Simulation time	13930342802 ps
CPU time	60.99 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:40:30 PM PDT 24
Peak memory	225868 kb
Host	smart-a364c6eb-209c-47f2-9c76-1af8b45f85a4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=890829188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_entropy_refresh.890829188 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/36.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/36.kmac_error.3024280311
Short name	T367
Test name
Test status
Simulation time	3509233002 ps
CPU time	263.65 seconds
Started	Jun 13 12:39:23 PM PDT 24
Finished	Jun 13 12:43:47 PM PDT 24
Peak memory	252372 kb
Host	smart-61e9cab3-8c88-426f-9625-774995abef17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3024280311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.3024280311 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_error/latest

Test location	/workspace/coverage/default/36.kmac_key_error.317829010
Short name	T517
Test name
Test status
Simulation time	1806552410 ps
CPU time	5.19 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:39:34 PM PDT 24
Peak memory	207504 kb
Host	smart-e27c0a7e-e5b7-4b26-b63c-af980eff0d57
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317829010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.317829010 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_key_error/latest

Test location	/workspace/coverage/default/36.kmac_lc_escalation.532446387
Short name	T415
Test name
Test status
Simulation time	35804235 ps
CPU time	1.21 seconds
Started	Jun 13 12:39:23 PM PDT 24
Finished	Jun 13 12:39:25 PM PDT 24
Peak memory	215704 kb
Host	smart-d1bb781c-f536-4809-82d7-60f6a264f010
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532446387 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.532446387 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/36.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/36.kmac_long_msg_and_output.2279906047
Short name	T427
Test name
Test status
Simulation time	80702430621 ps
CPU time	1736.68 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 01:08:16 PM PDT 24
Peak memory	377476 kb
Host	smart-ce0a2312-c123-434a-ac4c-977e8d7ded3a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279906047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a nd_output.2279906047 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/36.kmac_sideload.4254661660
Short name	T872
Test name
Test status
Simulation time	4186236640 ps
CPU time	326.38 seconds
Started	Jun 13 12:39:15 PM PDT 24
Finished	Jun 13 12:44:42 PM PDT 24
Peak memory	248320 kb
Host	smart-5c9457a2-5fc0-46a0-b623-725c4e3757de
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254661660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.4254661660 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_sideload/latest

Test location	/workspace/coverage/default/36.kmac_smoke.66196065
Short name	T215
Test name
Test status
Simulation time	186052959 ps
CPU time	9.72 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:39:28 PM PDT 24
Peak memory	217988 kb
Host	smart-4e5b18b5-bb83-4fcb-98d5-4a8bd807b12f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=66196065 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.66196065 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_smoke/latest

Test location	/workspace/coverage/default/36.kmac_stress_all.1265436896
Short name	T418
Test name
Test status
Simulation time	2373912355 ps
CPU time	45.63 seconds
Started	Jun 13 12:39:25 PM PDT 24
Finished	Jun 13 12:40:11 PM PDT 24
Peak memory	226464 kb
Host	smart-0aaeb39a-6cfd-4b17-a3cd-e8e3835ba5db
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1265436896 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all.1265436896 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all/latest

Test location	/workspace/coverage/default/36.kmac_stress_all_with_rand_reset.499814546
Short name	T33
Test name
Test status
Simulation time	50885902946 ps
CPU time	436.81 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:46:46 PM PDT 24
Peak memory	256804 kb
Host	smart-4f80b248-c4fd-4723-a6af-44e8c49fd59c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=499814546 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.499814546 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac.3250172156
Short name	T268
Test name
Test status
Simulation time	243032067 ps
CPU time	4.56 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 12:39:24 PM PDT 24
Peak memory	215832 kb
Host	smart-25a70220-9ce9-493f-90e2-6a42371bb2eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250172156 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 36.kmac_test_vectors_kmac.3250172156 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_kmac_xof.3841884696
Short name	T516
Test name
Test status
Simulation time	493893933 ps
CPU time	5.11 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 12:39:22 PM PDT 24
Peak memory	215768 kb
Host	smart-c05c341b-ac93-4913-b567-4a1adc331360
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841884696 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_kmac_xof.3841884696 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_224.111656231
Short name	T216
Test name
Test status
Simulation time	99235715816 ps
CPU time	1459.07 seconds
Started	Jun 13 12:39:21 PM PDT 24
Finished	Jun 13 01:03:42 PM PDT 24
Peak memory	392908 kb
Host	smart-fc97318a-9dfd-4769-a942-62ff2f7735c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=111656231 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.111656231 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_256.976926190
Short name	T866
Test name
Test status
Simulation time	36266474494 ps
CPU time	1457.75 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 01:03:36 PM PDT 24
Peak memory	375352 kb
Host	smart-2dddbf7f-cfd3-46aa-a059-153d73ffa8a1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=976926190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.976926190 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_384.2931803100
Short name	T756
Test name
Test status
Simulation time	48351034041 ps
CPU time	1330.26 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 01:01:29 PM PDT 24
Peak memory	329280 kb
Host	smart-4ce3a3d8-6b87-4d68-b904-19c1f0a25a8a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2931803100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.2931803100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_sha3_512.741220580
Short name	T996
Test name
Test status
Simulation time	29875006587 ps
CPU time	756.94 seconds
Started	Jun 13 12:39:18 PM PDT 24
Finished	Jun 13 12:51:56 PM PDT 24
Peak memory	295440 kb
Host	smart-2930de4f-c03d-4a22-86c9-1ccfefbff63c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=741220580 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.741220580 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_128.3196653382
Short name	T14
Test name
Test status
Simulation time	171534084374 ps
CPU time	4544.35 seconds
Started	Jun 13 12:39:16 PM PDT 24
Finished	Jun 13 01:55:02 PM PDT 24
Peak memory	646812 kb
Host	smart-c12155f9-6b54-4dcc-9e72-3e23eebb2da4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3196653382 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.3196653382 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/36.kmac_test_vectors_shake_256.4138465519
Short name	T492
Test name
Test status
Simulation time	46143808767 ps
CPU time	3374.41 seconds
Started	Jun 13 12:39:17 PM PDT 24
Finished	Jun 13 01:35:33 PM PDT 24
Peak memory	571672 kb
Host	smart-9079d2d8-b26f-4ebd-b6d9-348d0af26a9a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4138465519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.4138465519 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/36.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/37.kmac_alert_test.1698359444
Short name	T489
Test name
Test status
Simulation time	93808718 ps
CPU time	0.72 seconds
Started	Jun 13 12:39:35 PM PDT 24
Finished	Jun 13 12:39:37 PM PDT 24
Peak memory	205232 kb
Host	smart-21738d71-a32a-49a9-822c-a9e1b1346049
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698359444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.1698359444 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_alert_test/latest

Test location	/workspace/coverage/default/37.kmac_app.4285259630
Short name	T554
Test name
Test status
Simulation time	23882079592 ps
CPU time	279.84 seconds
Started	Jun 13 12:39:37 PM PDT 24
Finished	Jun 13 12:44:17 PM PDT 24
Peak memory	244908 kb
Host	smart-c508bee2-8560-43c7-b2da-e55eeb6ebcb1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285259630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.4285259630 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_app/latest

Test location	/workspace/coverage/default/37.kmac_burst_write.835811249
Short name	T709
Test name
Test status
Simulation time	21822699173 ps
CPU time	442.92 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:46:53 PM PDT 24
Peak memory	229336 kb
Host	smart-bdd96614-0258-4e8a-9d70-44e6cde7f874
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=835811249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.835811249 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_burst_write/latest

Test location	/workspace/coverage/default/37.kmac_entropy_refresh.3838311963
Short name	T1037
Test name
Test status
Simulation time	287655955 ps
CPU time	5.44 seconds
Started	Jun 13 12:39:39 PM PDT 24
Finished	Jun 13 12:39:45 PM PDT 24
Peak memory	215792 kb
Host	smart-a4325c7f-3361-4227-8dfa-d58f95835d89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3838311963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3838311963 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/37.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/37.kmac_error.325591270
Short name	T973
Test name
Test status
Simulation time	45046197790 ps
CPU time	392.8 seconds
Started	Jun 13 12:39:36 PM PDT 24
Finished	Jun 13 12:46:09 PM PDT 24
Peak memory	264956 kb
Host	smart-a16baba9-858f-4f40-a17d-cd45ec7f8e88
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325591270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.325591270 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_error/latest

Test location	/workspace/coverage/default/37.kmac_key_error.3006448001
Short name	T631
Test name
Test status
Simulation time	2013256421 ps
CPU time	10.95 seconds
Started	Jun 13 12:39:35 PM PDT 24
Finished	Jun 13 12:39:46 PM PDT 24
Peak memory	207504 kb
Host	smart-cf9de23b-7a9d-4858-ad4a-274c0b0ba202
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3006448001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.3006448001 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_key_error/latest

Test location	/workspace/coverage/default/37.kmac_lc_escalation.1710943785
Short name	T581
Test name
Test status
Simulation time	165241556 ps
CPU time	1.43 seconds
Started	Jun 13 12:39:39 PM PDT 24
Finished	Jun 13 12:39:41 PM PDT 24
Peak memory	215736 kb
Host	smart-f0ee4391-7774-4afc-a740-23d26bf90ba7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1710943785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.1710943785 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/37.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/37.kmac_long_msg_and_output.3047720312
Short name	T319
Test name
Test status
Simulation time	170115633527 ps
CPU time	880.22 seconds
Started	Jun 13 12:39:30 PM PDT 24
Finished	Jun 13 12:54:11 PM PDT 24
Peak memory	300492 kb
Host	smart-3c568671-734d-464d-ab2c-f4ef0d93a5d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047720312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a nd_output.3047720312 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/37.kmac_sideload.4133602971
Short name	T1027
Test name
Test status
Simulation time	4118285432 ps
CPU time	170.49 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:42:20 PM PDT 24
Peak memory	234800 kb
Host	smart-ce4d9b04-e31e-46ed-bf9b-64adbd3bbf96
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133602971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.4133602971 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_sideload/latest

Test location	/workspace/coverage/default/37.kmac_smoke.3736634995
Short name	T485
Test name
Test status
Simulation time	16162757953 ps
CPU time	67.05 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:40:37 PM PDT 24
Peak memory	224032 kb
Host	smart-724eabdf-996c-4632-b4f0-711f979791bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3736634995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.3736634995 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_smoke/latest

Test location	/workspace/coverage/default/37.kmac_stress_all.2394470294
Short name	T665
Test name
Test status
Simulation time	21312634653 ps
CPU time	721.72 seconds
Started	Jun 13 12:39:38 PM PDT 24
Finished	Jun 13 12:51:40 PM PDT 24
Peak memory	297956 kb
Host	smart-52353079-bb6f-47ee-9ed2-cb7c36bd21ac
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2394470294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_stress_all.2394470294 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_stress_all/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac.3672560019
Short name	T943
Test name
Test status
Simulation time	170027309 ps
CPU time	4.71 seconds
Started	Jun 13 12:39:28 PM PDT 24
Finished	Jun 13 12:39:33 PM PDT 24
Peak memory	215884 kb
Host	smart-e40ec1a0-bdfc-4e2c-9c6c-04c7edd73033
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672560019 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 37.kmac_test_vectors_kmac.3672560019 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_kmac_xof.110706474
Short name	T423
Test name
Test status
Simulation time	811409109 ps
CPU time	4.44 seconds
Started	Jun 13 12:39:31 PM PDT 24
Finished	Jun 13 12:39:36 PM PDT 24
Peak memory	215756 kb
Host	smart-047008cc-8d45-449d-a8d8-b90208965442
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110706474 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 37.kmac_test_vectors_kmac_xof.110706474 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_224.182876334
Short name	T211
Test name
Test status
Simulation time	362740456518 ps
CPU time	1751.88 seconds
Started	Jun 13 12:39:30 PM PDT 24
Finished	Jun 13 01:08:43 PM PDT 24
Peak memory	388484 kb
Host	smart-a3e30e19-f43c-4223-8667-ca929ce034d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=182876334 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.182876334 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_256.2232581866
Short name	T634
Test name
Test status
Simulation time	28636966637 ps
CPU time	1482.6 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 01:04:13 PM PDT 24
Peak memory	374528 kb
Host	smart-5afed6a6-a321-4df5-b876-0e9202ea6e25
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2232581866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.2232581866 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_384.701593943
Short name	T864
Test name
Test status
Simulation time	13748185502 ps
CPU time	1098.09 seconds
Started	Jun 13 12:39:32 PM PDT 24
Finished	Jun 13 12:57:50 PM PDT 24
Peak memory	332004 kb
Host	smart-837bd388-c0b0-4650-b8e5-712b4db09428
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=701593943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.701593943 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_sha3_512.366144502
Short name	T325
Test name
Test status
Simulation time	80973240951 ps
CPU time	814.76 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 12:53:05 PM PDT 24
Peak memory	294312 kb
Host	smart-c78a1833-2d20-493f-a999-4ca6ee91c746
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=366144502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.366144502 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_128.2477182364
Short name	T534
Test name
Test status
Simulation time	259295449328 ps
CPU time	5307.32 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 02:07:58 PM PDT 24
Peak memory	660656 kb
Host	smart-bc6713b6-af3a-43e6-80e5-30650ecfcd7a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2477182364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.2477182364 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/37.kmac_test_vectors_shake_256.3937560113
Short name	T230
Test name
Test status
Simulation time	178096989987 ps
CPU time	3088.52 seconds
Started	Jun 13 12:39:29 PM PDT 24
Finished	Jun 13 01:30:58 PM PDT 24
Peak memory	550460 kb
Host	smart-d6bfbe2f-4e1f-41ef-81aa-553b651351a7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3937560113 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3937560113 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/37.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/38.kmac_alert_test.1077998640
Short name	T250
Test name
Test status
Simulation time	50873718 ps
CPU time	0.76 seconds
Started	Jun 13 12:39:48 PM PDT 24
Finished	Jun 13 12:39:49 PM PDT 24
Peak memory	205268 kb
Host	smart-19fcb079-b22b-4cc9-b3b9-c36faa4d3374
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077998640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.1077998640 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_alert_test/latest

Test location	/workspace/coverage/default/38.kmac_app.4217882466
Short name	T727
Test name
Test status
Simulation time	432115782 ps
CPU time	9.96 seconds
Started	Jun 13 12:39:44 PM PDT 24
Finished	Jun 13 12:39:54 PM PDT 24
Peak memory	222372 kb
Host	smart-e7ffa28e-02d5-4e0c-aad1-297208b17488
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4217882466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.4217882466 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_app/latest

Test location	/workspace/coverage/default/38.kmac_burst_write.3791011077
Short name	T916
Test name
Test status
Simulation time	20218596205 ps
CPU time	513.91 seconds
Started	Jun 13 12:39:38 PM PDT 24
Finished	Jun 13 12:48:12 PM PDT 24
Peak memory	229544 kb
Host	smart-45cb0477-0695-42a7-a849-19a540004a60
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3791011077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3791011077 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_burst_write/latest

Test location	/workspace/coverage/default/38.kmac_entropy_refresh.2139959970
Short name	T732
Test name
Test status
Simulation time	17500658061 ps
CPU time	170.31 seconds
Started	Jun 13 12:39:44 PM PDT 24
Finished	Jun 13 12:42:35 PM PDT 24
Peak memory	237224 kb
Host	smart-ecd5570e-9603-4f39-92e1-2d45e15ef149
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2139959970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.2139959970 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/38.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/38.kmac_error.2022076721
Short name	T381
Test name
Test status
Simulation time	883632889 ps
CPU time	15.53 seconds
Started	Jun 13 12:39:42 PM PDT 24
Finished	Jun 13 12:39:58 PM PDT 24
Peak memory	224648 kb
Host	smart-7516fe1f-a7ec-4d60-9038-ff1bbae61425
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2022076721 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.2022076721 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_error/latest

Test location	/workspace/coverage/default/38.kmac_key_error.884761312
Short name	T334
Test name
Test status
Simulation time	18800288785 ps
CPU time	8.08 seconds
Started	Jun 13 12:39:43 PM PDT 24
Finished	Jun 13 12:39:52 PM PDT 24
Peak memory	207576 kb
Host	smart-d23c54f0-fd68-4407-8ebe-1b3cda7c9217
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=884761312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.884761312 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_key_error/latest

Test location	/workspace/coverage/default/38.kmac_lc_escalation.3842142333
Short name	T293
Test name
Test status
Simulation time	92835273 ps
CPU time	1.3 seconds
Started	Jun 13 12:39:43 PM PDT 24
Finished	Jun 13 12:39:45 PM PDT 24
Peak memory	215648 kb
Host	smart-381e2779-324d-4398-8ea9-f313c9fe4302
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3842142333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3842142333 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/38.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/38.kmac_long_msg_and_output.1045693100
Short name	T698
Test name
Test status
Simulation time	26750777676 ps
CPU time	2311.7 seconds
Started	Jun 13 12:39:39 PM PDT 24
Finished	Jun 13 01:18:12 PM PDT 24
Peak memory	476552 kb
Host	smart-fac7994d-b4ac-4f7c-bc3a-fde10815abb2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045693100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a nd_output.1045693100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/38.kmac_sideload.893628659
Short name	T794
Test name
Test status
Simulation time	4833273031 ps
CPU time	62.2 seconds
Started	Jun 13 12:39:36 PM PDT 24
Finished	Jun 13 12:40:39 PM PDT 24
Peak memory	225076 kb
Host	smart-3b9dca10-7ab0-407f-b78b-461040907a55
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893628659 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.893628659 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_sideload/latest

Test location	/workspace/coverage/default/38.kmac_smoke.3142896953
Short name	T344
Test name
Test status
Simulation time	2923306100 ps
CPU time	31.04 seconds
Started	Jun 13 12:39:39 PM PDT 24
Finished	Jun 13 12:40:10 PM PDT 24
Peak memory	219272 kb
Host	smart-8c3dcbab-4a07-4766-9376-15f496610dac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3142896953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.3142896953 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_smoke/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac.1065007493
Short name	T225
Test name
Test status
Simulation time	64539164 ps
CPU time	3.99 seconds
Started	Jun 13 12:39:44 PM PDT 24
Finished	Jun 13 12:39:49 PM PDT 24
Peak memory	215768 kb
Host	smart-fea70caf-002a-4e7d-85e6-d4eb44747401
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065007493 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 38.kmac_test_vectors_kmac.1065007493 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_kmac_xof.49865472
Short name	T595
Test name
Test status
Simulation time	226126886 ps
CPU time	4.7 seconds
Started	Jun 13 12:39:42 PM PDT 24
Finished	Jun 13 12:39:47 PM PDT 24
Peak memory	215760 kb
Host	smart-30ecb765-6cdc-4f9e-84d6-9eb7cf9f2f73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49865472 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 38.kmac_test_vectors_kmac_xof.49865472 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_224.2007699774
Short name	T404
Test name
Test status
Simulation time	37751789644 ps
CPU time	1548.49 seconds
Started	Jun 13 12:39:43 PM PDT 24
Finished	Jun 13 01:05:33 PM PDT 24
Peak memory	378320 kb
Host	smart-7b360ee5-4985-4f63-826e-10059452f6f7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2007699774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.2007699774 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_256.4161382979
Short name	T1073
Test name
Test status
Simulation time	126100730855 ps
CPU time	1636.19 seconds
Started	Jun 13 12:39:38 PM PDT 24
Finished	Jun 13 01:06:55 PM PDT 24
Peak memory	378984 kb
Host	smart-e89af92d-2cd5-4b45-b69c-819be55470cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4161382979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.4161382979 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_384.494619795
Short name	T507
Test name
Test status
Simulation time	48003847766 ps
CPU time	1254.25 seconds
Started	Jun 13 12:39:43 PM PDT 24
Finished	Jun 13 01:00:37 PM PDT 24
Peak memory	329848 kb
Host	smart-718e7574-1222-4a1d-b65c-8d4dc1992c9a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=494619795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.494619795 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_sha3_512.3693752184
Short name	T419
Test name
Test status
Simulation time	48103134370 ps
CPU time	914.24 seconds
Started	Jun 13 12:39:44 PM PDT 24
Finished	Jun 13 12:54:59 PM PDT 24
Peak memory	291640 kb
Host	smart-68b99871-399f-4eb0-a8da-09ea706bcc0a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3693752184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.3693752184 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_128.4035219502
Short name	T18
Test name
Test status
Simulation time	447445955816 ps
CPU time	4934.82 seconds
Started	Jun 13 12:39:43 PM PDT 24
Finished	Jun 13 02:01:58 PM PDT 24
Peak memory	655348 kb
Host	smart-55317e16-9a6d-4186-8579-0bb241fc8858
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4035219502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.4035219502 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/38.kmac_test_vectors_shake_256.1907437111
Short name	T819
Test name
Test status
Simulation time	473190100730 ps
CPU time	3518.67 seconds
Started	Jun 13 12:39:44 PM PDT 24
Finished	Jun 13 01:38:23 PM PDT 24
Peak memory	547832 kb
Host	smart-f238d2ce-0faa-4276-a795-58dc2f520880
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1907437111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.1907437111 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/38.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/39.kmac_alert_test.1609379995
Short name	T1038
Test name
Test status
Simulation time	15963091 ps
CPU time	0.81 seconds
Started	Jun 13 12:40:01 PM PDT 24
Finished	Jun 13 12:40:02 PM PDT 24
Peak memory	205232 kb
Host	smart-8a91adb2-3d2f-41d4-98cf-1bf26864e5ac
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609379995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.1609379995 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_alert_test/latest

Test location	/workspace/coverage/default/39.kmac_app.2127507644
Short name	T91
Test name
Test status
Simulation time	3069863346 ps
CPU time	82.24 seconds
Started	Jun 13 12:39:54 PM PDT 24
Finished	Jun 13 12:41:17 PM PDT 24
Peak memory	227072 kb
Host	smart-423abbbe-fb00-4d9a-ad9e-0bf95c54d8f7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127507644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.2127507644 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_app/latest

Test location	/workspace/coverage/default/39.kmac_burst_write.2918699874
Short name	T604
Test name
Test status
Simulation time	24842556774 ps
CPU time	624.11 seconds
Started	Jun 13 12:39:47 PM PDT 24
Finished	Jun 13 12:50:11 PM PDT 24
Peak memory	231364 kb
Host	smart-5f4f6697-73a1-4589-987a-02d9ef346a5c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2918699874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.2918699874 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_burst_write/latest

Test location	/workspace/coverage/default/39.kmac_entropy_refresh.1747993420
Short name	T349
Test name
Test status
Simulation time	3613682387 ps
CPU time	56.27 seconds
Started	Jun 13 12:39:55 PM PDT 24
Finished	Jun 13 12:40:52 PM PDT 24
Peak memory	225192 kb
Host	smart-fcd05f34-5abc-4c44-944d-bc61d95504fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1747993420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1747993420 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/39.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/39.kmac_error.3204725909
Short name	T455
Test name
Test status
Simulation time	15816244636 ps
CPU time	95.94 seconds
Started	Jun 13 12:39:55 PM PDT 24
Finished	Jun 13 12:41:32 PM PDT 24
Peak memory	240516 kb
Host	smart-a1ee5c51-c51b-448f-acd2-dafcff75ad33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3204725909 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.3204725909 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_error/latest

Test location	/workspace/coverage/default/39.kmac_key_error.2816314945
Short name	T590
Test name
Test status
Simulation time	2785040320 ps
CPU time	7.59 seconds
Started	Jun 13 12:40:01 PM PDT 24
Finished	Jun 13 12:40:09 PM PDT 24
Peak memory	215632 kb
Host	smart-f2d384d0-e592-4bab-8e41-cf33def61e51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2816314945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.2816314945 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_key_error/latest

Test location	/workspace/coverage/default/39.kmac_lc_escalation.1592126612
Short name	T923
Test name
Test status
Simulation time	326981614 ps
CPU time	1.45 seconds
Started	Jun 13 12:40:02 PM PDT 24
Finished	Jun 13 12:40:04 PM PDT 24
Peak memory	215648 kb
Host	smart-e5c2ee58-771f-4941-9f2f-efda6c57b881
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1592126612 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.1592126612 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/39.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/39.kmac_long_msg_and_output.2449207706
Short name	T671
Test name
Test status
Simulation time	359580063720 ps
CPU time	2260.3 seconds
Started	Jun 13 12:39:52 PM PDT 24
Finished	Jun 13 01:17:33 PM PDT 24
Peak memory	431292 kb
Host	smart-75483d1f-8c22-4e5a-ad82-1cd575f16ea4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449207706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a nd_output.2449207706 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/39.kmac_sideload.1737872085
Short name	T918
Test name
Test status
Simulation time	2351998356 ps
CPU time	42.76 seconds
Started	Jun 13 12:39:48 PM PDT 24
Finished	Jun 13 12:40:31 PM PDT 24
Peak memory	222560 kb
Host	smart-a46fb446-55b5-46a2-b00a-fff0f0c3cbdb
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737872085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.1737872085 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_sideload/latest

Test location	/workspace/coverage/default/39.kmac_smoke.1853004474
Short name	T762
Test name
Test status
Simulation time	666068151 ps
CPU time	7.75 seconds
Started	Jun 13 12:39:46 PM PDT 24
Finished	Jun 13 12:39:54 PM PDT 24
Peak memory	218716 kb
Host	smart-ab4ceab6-ed10-408c-b640-71c482ecf9e4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853004474 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.1853004474 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_smoke/latest

Test location	/workspace/coverage/default/39.kmac_stress_all.2972820796
Short name	T594
Test name
Test status
Simulation time	124847770992 ps
CPU time	1306.59 seconds
Started	Jun 13 12:40:05 PM PDT 24
Finished	Jun 13 01:01:53 PM PDT 24
Peak memory	387144 kb
Host	smart-922d4566-4448-4c22-a794-c197bd0f58b4
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2972820796 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.2972820796 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_stress_all/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac.1279140942
Short name	T661
Test name
Test status
Simulation time	345771757 ps
CPU time	4.63 seconds
Started	Jun 13 12:39:57 PM PDT 24
Finished	Jun 13 12:40:02 PM PDT 24
Peak memory	215696 kb
Host	smart-f2929472-d1a3-4335-a5dc-80ecd9a640b8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279140942 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 39.kmac_test_vectors_kmac.1279140942 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_kmac_xof.2086620469
Short name	T939
Test name
Test status
Simulation time	978693890 ps
CPU time	5.05 seconds
Started	Jun 13 12:39:56 PM PDT 24
Finished	Jun 13 12:40:01 PM PDT 24
Peak memory	215704 kb
Host	smart-3e51888f-ca51-4141-8ece-6eeedc41e13b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086620469 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_kmac_xof.2086620469 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_224.2264399735
Short name	T373
Test name
Test status
Simulation time	103558233731 ps
CPU time	1548.43 seconds
Started	Jun 13 12:39:48 PM PDT 24
Finished	Jun 13 01:05:37 PM PDT 24
Peak memory	388680 kb
Host	smart-8c78d89c-830e-4e1c-9916-22a57a6b3a6c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2264399735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2264399735 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_256.1264260312
Short name	T340
Test name
Test status
Simulation time	36703723112 ps
CPU time	1422.27 seconds
Started	Jun 13 12:39:55 PM PDT 24
Finished	Jun 13 01:03:38 PM PDT 24
Peak memory	371900 kb
Host	smart-d505fdc9-6c3a-49ff-84fd-30b006494559
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1264260312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.1264260312 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_384.1187921713
Short name	T383
Test name
Test status
Simulation time	221296808048 ps
CPU time	1399.5 seconds
Started	Jun 13 12:39:55 PM PDT 24
Finished	Jun 13 01:03:15 PM PDT 24
Peak memory	328972 kb
Host	smart-1c669b70-3912-4c66-a81a-4d634c557207
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1187921713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.1187921713 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_sha3_512.1015738123
Short name	T286
Test name
Test status
Simulation time	37532708828 ps
CPU time	784.83 seconds
Started	Jun 13 12:39:55 PM PDT 24
Finished	Jun 13 12:53:00 PM PDT 24
Peak memory	292888 kb
Host	smart-d6860ebb-f30c-474d-a54e-c20cd80c3718
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1015738123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.1015738123 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_128.4028028357
Short name	T894
Test name
Test status
Simulation time	1013483156212 ps
CPU time	5251.38 seconds
Started	Jun 13 12:39:56 PM PDT 24
Finished	Jun 13 02:07:28 PM PDT 24
Peak memory	638292 kb
Host	smart-0e8e8460-d2a3-4f2f-842d-abe1b520243c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4028028357 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.4028028357 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/39.kmac_test_vectors_shake_256.928766096
Short name	T886
Test name
Test status
Simulation time	558143716193 ps
CPU time	4159.41 seconds
Started	Jun 13 12:39:56 PM PDT 24
Finished	Jun 13 01:49:16 PM PDT 24
Peak memory	559888 kb
Host	smart-e65b0ba7-0af2-4c22-905b-7286922d9854
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=928766096 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.928766096 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/39.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/4.kmac_alert_test.3790112222
Short name	T358
Test name
Test status
Simulation time	48831307 ps
CPU time	0.78 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:19 PM PDT 24
Peak memory	205232 kb
Host	smart-1e89c6d7-996c-4e80-80e4-d57cd4f2971e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790112222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3790112222 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_alert_test/latest

Test location	/workspace/coverage/default/4.kmac_app.4184244445
Short name	T687
Test name
Test status
Simulation time	54698576 ps
CPU time	2.74 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:21 PM PDT 24
Peak memory	221176 kb
Host	smart-558ed396-363a-4368-a533-c9d0eadadfd2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4184244445 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.4184244445 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_app/latest

Test location	/workspace/coverage/default/4.kmac_app_with_partial_data.2715460869
Short name	T456
Test name
Test status
Simulation time	8346873910 ps
CPU time	158.02 seconds
Started	Jun 13 12:37:02 PM PDT 24
Finished	Jun 13 12:39:41 PM PDT 24
Peak memory	233564 kb
Host	smart-1862f43f-fe36-470d-8712-a77d60a2f01e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715460869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.2715460869 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/4.kmac_burst_write.3021890376
Short name	T544
Test name
Test status
Simulation time	149689562533 ps
CPU time	881.56 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:51:50 PM PDT 24
Peak memory	232204 kb
Host	smart-a59e7f40-d709-49e4-aac2-8c1fbbe0677a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3021890376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3021890376 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_burst_write/latest

Test location	/workspace/coverage/default/4.kmac_edn_timeout_error.3689756364
Short name	T931
Test name
Test status
Simulation time	1872001099 ps
CPU time	35.16 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:37:44 PM PDT 24
Peak memory	223712 kb
Host	smart-79e34c4a-125d-43b6-8c4b-94954ab6d418
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3689756364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3689756364 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_mode_error.3582454671
Short name	T425
Test name
Test status
Simulation time	1455473571 ps
CPU time	30.77 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:37:54 PM PDT 24
Peak memory	223756 kb
Host	smart-fa2109d6-f771-44e6-b561-3671236bf31c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3582454671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.3582454671 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_ready_error.1970642007
Short name	T796
Test name
Test status
Simulation time	1222280393 ps
CPU time	14.64 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:37:36 PM PDT 24
Peak memory	223852 kb
Host	smart-7350ea47-761e-4b20-b1bd-5740ec7a2043
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1970642007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1970642007 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/4.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/4.kmac_entropy_refresh.1590323497
Short name	T191
Test name
Test status
Simulation time	15519949269 ps
CPU time	295.58 seconds
Started	Jun 13 12:38:02 PM PDT 24
Finished	Jun 13 12:42:58 PM PDT 24
Peak memory	241908 kb
Host	smart-f54538ac-9baa-4e4a-be05-4cb3b249e4d0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590323497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.1590323497 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/4.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/4.kmac_error.2448441083
Short name	T629
Test name
Test status
Simulation time	899461336 ps
CPU time	32.15 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:38:06 PM PDT 24
Peak memory	232200 kb
Host	smart-2182537b-c35c-44e1-bd5c-42fbdd02990d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2448441083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2448441083 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_error/latest

Test location	/workspace/coverage/default/4.kmac_key_error.1110527992
Short name	T406
Test name
Test status
Simulation time	4118288831 ps
CPU time	8.29 seconds
Started	Jun 13 12:37:29 PM PDT 24
Finished	Jun 13 12:37:38 PM PDT 24
Peak memory	207544 kb
Host	smart-c2b19f22-a350-4742-a156-8a898c55b2e5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110527992 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.1110527992 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_key_error/latest

Test location	/workspace/coverage/default/4.kmac_lc_escalation.1609991865
Short name	T814
Test name
Test status
Simulation time	36672641 ps
CPU time	1.16 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 12:37:25 PM PDT 24
Peak memory	215628 kb
Host	smart-244d61ff-cd48-439c-b965-158eaaa42905
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1609991865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.1609991865 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/4.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/4.kmac_long_msg_and_output.4026919873
Short name	T832
Test name
Test status
Simulation time	193025548996 ps
CPU time	1056.19 seconds
Started	Jun 13 12:37:05 PM PDT 24
Finished	Jun 13 12:54:43 PM PDT 24
Peak memory	318124 kb
Host	smart-773ef66d-3267-4487-9eeb-a205162bb9df
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026919873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an d_output.4026919873 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/4.kmac_mubi.369444026
Short name	T851
Test name
Test status
Simulation time	54658327000 ps
CPU time	260.46 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:41:42 PM PDT 24
Peak memory	243408 kb
Host	smart-6c5cbdd1-777c-4614-acf4-7c1f124e9830
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=369444026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.369444026 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_mubi/latest

Test location	/workspace/coverage/default/4.kmac_sec_cm.1019892544
Short name	T7
Test name
Test status
Simulation time	12105393654 ps
CPU time	80.2 seconds
Started	Jun 13 12:37:26 PM PDT 24
Finished	Jun 13 12:38:47 PM PDT 24
Peak memory	278500 kb
Host	smart-f6ac2b6b-3393-46b8-8794-466b4fd5f70d
User	root
Command	/workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019892544 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.1019892544 +enable_maski ng=0 +sw_key_masked=0
Directory	/workspace/4.kmac_sec_cm/latest

Test location	/workspace/coverage/default/4.kmac_sideload.3209635412
Short name	T433
Test name
Test status
Simulation time	3620954697 ps
CPU time	264.58 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:41:45 PM PDT 24
Peak memory	243600 kb
Host	smart-1cfda0f4-b159-49e3-a917-73ccea0f3bfd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209635412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3209635412 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_sideload/latest

Test location	/workspace/coverage/default/4.kmac_smoke.2324907205
Short name	T401
Test name
Test status
Simulation time	1005105961 ps
CPU time	25.75 seconds
Started	Jun 13 12:37:05 PM PDT 24
Finished	Jun 13 12:37:31 PM PDT 24
Peak memory	215704 kb
Host	smart-1e89b3c5-b695-4f37-bfca-8ac368b9204a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2324907205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.2324907205 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_smoke/latest

Test location	/workspace/coverage/default/4.kmac_stress_all.554185742
Short name	T571
Test name
Test status
Simulation time	9178807931 ps
CPU time	147.36 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:39:40 PM PDT 24
Peak memory	253376 kb
Host	smart-b1996e80-cea3-475d-b3a2-826c4d391c4f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=554185742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.554185742 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all/latest

Test location	/workspace/coverage/default/4.kmac_stress_all_with_rand_reset.1206547100
Short name	T821
Test name
Test status
Simulation time	44056479302 ps
CPU time	873.08 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:51:55 PM PDT 24
Peak memory	287264 kb
Host	smart-9511505f-376f-4f99-b671-c6b030cb811f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1206547100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.1206547100 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac.1621828362
Short name	T384
Test name
Test status
Simulation time	280108630 ps
CPU time	3.7 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:37:15 PM PDT 24
Peak memory	215816 kb
Host	smart-cbda946b-c2b2-48e0-b736-692d3c878872
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621828362 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 4.kmac_test_vectors_kmac.1621828362 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3659440076
Short name	T815
Test name
Test status
Simulation time	674716789 ps
CPU time	4.46 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:37:14 PM PDT 24
Peak memory	215780 kb
Host	smart-c4f2c856-f05d-446f-af74-539e1099ba06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659440076 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3659440076 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_224.2121904199
Short name	T205
Test name
Test status
Simulation time	386791250534 ps
CPU time	1917.95 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 01:09:29 PM PDT 24
Peak memory	391124 kb
Host	smart-f89c3039-ffb8-48e3-b40e-8c04986c6fb3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2121904199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2121904199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_256.1703381754
Short name	T849
Test name
Test status
Simulation time	236519395162 ps
CPU time	1497.71 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 01:02:11 PM PDT 24
Peak memory	362004 kb
Host	smart-1a068c1c-b97b-4f33-af71-62f4e88abcab
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1703381754 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.1703381754 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_384.2300988264
Short name	T394
Test name
Test status
Simulation time	18901591429 ps
CPU time	1120.14 seconds
Started	Jun 13 12:37:01 PM PDT 24
Finished	Jun 13 12:55:43 PM PDT 24
Peak memory	338708 kb
Host	smart-3dc964ce-f688-453e-947b-3d7e57460bf3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2300988264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.2300988264 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_sha3_512.4062238157
Short name	T878
Test name
Test status
Simulation time	32135268496 ps
CPU time	822.3 seconds
Started	Jun 13 12:37:05 PM PDT 24
Finished	Jun 13 12:50:48 PM PDT 24
Peak memory	292400 kb
Host	smart-fcf39a3f-a75f-4098-b2ba-c795311d6396
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4062238157 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.4062238157 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_128.4290541584
Short name	T70
Test name
Test status
Simulation time	176422204228 ps
CPU time	4808.34 seconds
Started	Jun 13 12:36:58 PM PDT 24
Finished	Jun 13 01:57:08 PM PDT 24
Peak memory	656684 kb
Host	smart-d8896db0-02bc-4b34-8a79-ea9bec9a9c43
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4290541584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.4290541584 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/4.kmac_test_vectors_shake_256.1129494518
Short name	T479
Test name
Test status
Simulation time	289184368537 ps
CPU time	3400.77 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 01:34:03 PM PDT 24
Peak memory	563660 kb
Host	smart-6e42b535-6e82-4431-8569-7ec3d12f820d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1129494518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.1129494518 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/4.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/40.kmac_alert_test.1102725802
Short name	T221
Test name
Test status
Simulation time	18686902 ps
CPU time	0.83 seconds
Started	Jun 13 12:40:10 PM PDT 24
Finished	Jun 13 12:40:12 PM PDT 24
Peak memory	205232 kb
Host	smart-7fd303b4-7007-450b-a6c2-279bdd6be996
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102725802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.1102725802 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_alert_test/latest

Test location	/workspace/coverage/default/40.kmac_app.3915351495
Short name	T501
Test name
Test status
Simulation time	578197758 ps
CPU time	16.08 seconds
Started	Jun 13 12:40:11 PM PDT 24
Finished	Jun 13 12:40:27 PM PDT 24
Peak memory	224028 kb
Host	smart-89e68a25-fe30-4101-a16d-a0c755044c03
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3915351495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3915351495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_app/latest

Test location	/workspace/coverage/default/40.kmac_burst_write.1620828700
Short name	T710
Test name
Test status
Simulation time	4832039674 ps
CPU time	378.7 seconds
Started	Jun 13 12:40:01 PM PDT 24
Finished	Jun 13 12:46:20 PM PDT 24
Peak memory	228464 kb
Host	smart-5a68e744-4411-4d9f-879e-bfb7fd7a8f53
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1620828700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.1620828700 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_burst_write/latest

Test location	/workspace/coverage/default/40.kmac_entropy_refresh.970721423
Short name	T1028
Test name
Test status
Simulation time	17745948296 ps
CPU time	128.1 seconds
Started	Jun 13 12:40:12 PM PDT 24
Finished	Jun 13 12:42:20 PM PDT 24
Peak memory	233232 kb
Host	smart-a6cde4f4-a071-4680-8bed-4079ee9699f1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=970721423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.970721423 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/40.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/40.kmac_error.716148310
Short name	T513
Test name
Test status
Simulation time	1773177695 ps
CPU time	130.62 seconds
Started	Jun 13 12:40:09 PM PDT 24
Finished	Jun 13 12:42:20 PM PDT 24
Peak memory	240388 kb
Host	smart-a6f832c5-e2e1-49d2-8c7b-7430f8f5f60e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=716148310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.716148310 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_error/latest

Test location	/workspace/coverage/default/40.kmac_key_error.2840038110
Short name	T820
Test name
Test status
Simulation time	276390450 ps
CPU time	1.99 seconds
Started	Jun 13 12:40:10 PM PDT 24
Finished	Jun 13 12:40:13 PM PDT 24
Peak memory	207436 kb
Host	smart-e82c9b0e-47ff-4da0-8db7-8d453135f7d9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2840038110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.2840038110 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_key_error/latest

Test location	/workspace/coverage/default/40.kmac_lc_escalation.1540204552
Short name	T605
Test name
Test status
Simulation time	106431786 ps
CPU time	1.34 seconds
Started	Jun 13 12:40:08 PM PDT 24
Finished	Jun 13 12:40:10 PM PDT 24
Peak memory	220256 kb
Host	smart-67d13084-c320-42f3-911c-fc05fba02a42
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1540204552 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.1540204552 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/40.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/40.kmac_long_msg_and_output.159225097
Short name	T269
Test name
Test status
Simulation time	23337239421 ps
CPU time	492.3 seconds
Started	Jun 13 12:40:01 PM PDT 24
Finished	Jun 13 12:48:14 PM PDT 24
Peak memory	271032 kb
Host	smart-c001fb18-36c7-4dc8-8abc-eeddc398cfee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159225097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an d_output.159225097 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/40.kmac_sideload.1245772791
Short name	T536
Test name
Test status
Simulation time	14184001485 ps
CPU time	288.48 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 12:44:52 PM PDT 24
Peak memory	243560 kb
Host	smart-fc0a8905-bc5d-423f-9d0f-8c6f48aca8b8
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245772791 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.1245772791 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_sideload/latest

Test location	/workspace/coverage/default/40.kmac_smoke.3976634183
Short name	T706
Test name
Test status
Simulation time	701227671 ps
CPU time	32.92 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 12:40:37 PM PDT 24
Peak memory	218724 kb
Host	smart-3ef19b67-6f9c-48bf-a105-f2aa03a75115
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3976634183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.3976634183 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_smoke/latest

Test location	/workspace/coverage/default/40.kmac_stress_all.240533019
Short name	T726
Test name
Test status
Simulation time	113148104177 ps
CPU time	189.74 seconds
Started	Jun 13 12:40:10 PM PDT 24
Finished	Jun 13 12:43:20 PM PDT 24
Peak memory	241200 kb
Host	smart-f98362ad-c348-4986-b6db-d5fca502b99d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=240533019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.240533019 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_stress_all/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac.339730034
Short name	T296
Test name
Test status
Simulation time	228203829 ps
CPU time	4.56 seconds
Started	Jun 13 12:40:04 PM PDT 24
Finished	Jun 13 12:40:09 PM PDT 24
Peak memory	215864 kb
Host	smart-ea8e044e-394e-48ed-aa2c-4101d1a9ffe8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339730034 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 40.kmac_test_vectors_kmac.339730034 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1073900336
Short name	T676
Test name
Test status
Simulation time	310382935 ps
CPU time	3.91 seconds
Started	Jun 13 12:40:11 PM PDT 24
Finished	Jun 13 12:40:15 PM PDT 24
Peak memory	215836 kb
Host	smart-ec1999b2-464e-491e-a199-55667973d22e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073900336 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1073900336 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_224.786735087
Short name	T195
Test name
Test status
Simulation time	83768088677 ps
CPU time	1823.66 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 01:10:28 PM PDT 24
Peak memory	389912 kb
Host	smart-64c41fcd-4061-4644-8518-02240af67a6d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=786735087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.786735087 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_256.2447349798
Short name	T753
Test name
Test status
Simulation time	21462647970 ps
CPU time	1486.98 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 01:04:51 PM PDT 24
Peak memory	376008 kb
Host	smart-abbbcb26-f552-49da-abe8-ddff0244cabf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2447349798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.2447349798 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_384.366267377
Short name	T897
Test name
Test status
Simulation time	287887035607 ps
CPU time	1488.41 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 01:04:52 PM PDT 24
Peak memory	341844 kb
Host	smart-96676a4e-2a60-480d-b51d-3d2ba18f6fb1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=366267377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.366267377 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_sha3_512.3205851973
Short name	T746
Test name
Test status
Simulation time	10427145518 ps
CPU time	720.38 seconds
Started	Jun 13 12:40:01 PM PDT 24
Finished	Jun 13 12:52:02 PM PDT 24
Peak memory	290104 kb
Host	smart-1fb96096-d285-4869-b475-00b784a72d8a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3205851973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.3205851973 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_128.1679679446
Short name	T1043
Test name
Test status
Simulation time	177009662723 ps
CPU time	4491.66 seconds
Started	Jun 13 12:40:03 PM PDT 24
Finished	Jun 13 01:54:56 PM PDT 24
Peak memory	638656 kb
Host	smart-2770b3c8-636d-44dd-b8bc-dd6ca0f1cbcc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1679679446 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1679679446 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/40.kmac_test_vectors_shake_256.1697634312
Short name	T203
Test name
Test status
Simulation time	143311729451 ps
CPU time	3601.65 seconds
Started	Jun 13 12:40:00 PM PDT 24
Finished	Jun 13 01:40:02 PM PDT 24
Peak memory	555892 kb
Host	smart-436df911-97e3-4a81-adc9-072f2727cd82
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1697634312 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.1697634312 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/40.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/41.kmac_alert_test.2514152524
Short name	T525
Test name
Test status
Simulation time	65382427 ps
CPU time	0.78 seconds
Started	Jun 13 12:40:25 PM PDT 24
Finished	Jun 13 12:40:27 PM PDT 24
Peak memory	205072 kb
Host	smart-c06e06ed-4393-4708-baf7-cae86ae28a65
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514152524 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.2514152524 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_alert_test/latest

Test location	/workspace/coverage/default/41.kmac_app.568036275
Short name	T137
Test name
Test status
Simulation time	8087170348 ps
CPU time	180.23 seconds
Started	Jun 13 12:40:22 PM PDT 24
Finished	Jun 13 12:43:23 PM PDT 24
Peak memory	236776 kb
Host	smart-1d8e3750-b60b-4939-8895-15b2d5ffe328
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=568036275 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.568036275 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_app/latest

Test location	/workspace/coverage/default/41.kmac_burst_write.240801571
Short name	T713
Test name
Test status
Simulation time	7723847783 ps
CPU time	154.84 seconds
Started	Jun 13 12:40:15 PM PDT 24
Finished	Jun 13 12:42:51 PM PDT 24
Peak memory	225020 kb
Host	smart-3b858ffa-b239-4f57-bc06-5d5a49fe62f2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=240801571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.240801571 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_burst_write/latest

Test location	/workspace/coverage/default/41.kmac_entropy_refresh.621031636
Short name	T192
Test name
Test status
Simulation time	22427431981 ps
CPU time	366.66 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:46:30 PM PDT 24
Peak memory	247856 kb
Host	smart-cb6b239a-09ae-4e4f-afb0-7209bd1014bb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621031636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.621031636 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/41.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/41.kmac_error.2624241376
Short name	T839
Test name
Test status
Simulation time	14582486559 ps
CPU time	314.57 seconds
Started	Jun 13 12:40:22 PM PDT 24
Finished	Jun 13 12:45:37 PM PDT 24
Peak memory	254336 kb
Host	smart-bf6eb9a1-c1c2-4430-9663-c0d039460334
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624241376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2624241376 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_error/latest

Test location	/workspace/coverage/default/41.kmac_key_error.1818518490
Short name	T56
Test name
Test status
Simulation time	2196102287 ps
CPU time	2.96 seconds
Started	Jun 13 12:40:22 PM PDT 24
Finished	Jun 13 12:40:26 PM PDT 24
Peak memory	207496 kb
Host	smart-d1c5fbf2-2ee6-4da5-a0f3-0a8fe000036c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1818518490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.1818518490 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_key_error/latest

Test location	/workspace/coverage/default/41.kmac_lc_escalation.487911069
Short name	T410
Test name
Test status
Simulation time	918109813 ps
CPU time	22.6 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:40:46 PM PDT 24
Peak memory	229176 kb
Host	smart-f26edc6a-8bfd-4342-8b3f-c032d5d9b0c8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=487911069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.487911069 +enable_masking=0 +sw_key _masked=0
Directory	/workspace/41.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/41.kmac_long_msg_and_output.3947987252
Short name	T460
Test name
Test status
Simulation time	77642024929 ps
CPU time	1585.6 seconds
Started	Jun 13 12:40:16 PM PDT 24
Finished	Jun 13 01:06:42 PM PDT 24
Peak memory	362388 kb
Host	smart-bf8f9e8e-3b7b-45db-8060-edae6303ac2d
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947987252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_a nd_output.3947987252 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/41.kmac_sideload.1872768122
Short name	T593
Test name
Test status
Simulation time	46069870557 ps
CPU time	289.46 seconds
Started	Jun 13 12:40:15 PM PDT 24
Finished	Jun 13 12:45:05 PM PDT 24
Peak memory	243468 kb
Host	smart-27cab07f-c115-4c09-a664-1b11bd16bae0
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872768122 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.1872768122 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_sideload/latest

Test location	/workspace/coverage/default/41.kmac_smoke.1407732716
Short name	T998
Test name
Test status
Simulation time	2483473878 ps
CPU time	30.1 seconds
Started	Jun 13 12:40:18 PM PDT 24
Finished	Jun 13 12:40:49 PM PDT 24
Peak memory	216868 kb
Host	smart-f643b76b-1208-4fb4-8bbe-92e0b4ddd418
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1407732716 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1407732716 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_smoke/latest

Test location	/workspace/coverage/default/41.kmac_stress_all.11965295
Short name	T798
Test name
Test status
Simulation time	41030325958 ps
CPU time	1112.72 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:58:56 PM PDT 24
Peak memory	333272 kb
Host	smart-cc144db4-0588-41b6-85d2-0f81d4f00b88
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=11965295 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.11965295 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all/latest

Test location	/workspace/coverage/default/41.kmac_stress_all_with_rand_reset.2458591425
Short name	T952
Test name
Test status
Simulation time	454933672472 ps
CPU time	954.53 seconds
Started	Jun 13 12:40:24 PM PDT 24
Finished	Jun 13 12:56:19 PM PDT 24
Peak memory	265376 kb
Host	smart-747080f5-db08-45e9-b941-c872bcb68f5d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2458591425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.2458591425 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac.711616611
Short name	T555
Test name
Test status
Simulation time	235452285 ps
CPU time	3.59 seconds
Started	Jun 13 12:40:15 PM PDT 24
Finished	Jun 13 12:40:19 PM PDT 24
Peak memory	215676 kb
Host	smart-e7268772-d981-4dbf-983b-2fb5de6540d2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711616611 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 41.kmac_test_vectors_kmac.711616611 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2783207031
Short name	T607
Test name
Test status
Simulation time	250859504 ps
CPU time	4.1 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:40:28 PM PDT 24
Peak memory	215848 kb
Host	smart-0cfeb587-bc0e-4691-ac10-993aa063b363
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783207031 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2783207031 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_224.3198093128
Short name	T674
Test name
Test status
Simulation time	428352240549 ps
CPU time	1933.01 seconds
Started	Jun 13 12:40:14 PM PDT 24
Finished	Jun 13 01:12:28 PM PDT 24
Peak memory	397860 kb
Host	smart-1363dadf-93b2-4462-8dbb-c43b52b21776
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3198093128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.3198093128 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_256.3633018979
Short name	T901
Test name
Test status
Simulation time	444297706338 ps
CPU time	1996.36 seconds
Started	Jun 13 12:40:16 PM PDT 24
Finished	Jun 13 01:13:33 PM PDT 24
Peak memory	388112 kb
Host	smart-084e3e26-cb15-4030-a403-52ec8cd385fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3633018979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.3633018979 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_384.1257846037
Short name	T730
Test name
Test status
Simulation time	46048956631 ps
CPU time	1297.02 seconds
Started	Jun 13 12:40:14 PM PDT 24
Finished	Jun 13 01:01:52 PM PDT 24
Peak memory	329912 kb
Host	smart-34fb321d-0344-4653-af3e-ccd6db9e78b3
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1257846037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1257846037 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_sha3_512.954033746
Short name	T189
Test name
Test status
Simulation time	19544368801 ps
CPU time	757.3 seconds
Started	Jun 13 12:40:17 PM PDT 24
Finished	Jun 13 12:52:55 PM PDT 24
Peak memory	296640 kb
Host	smart-a46669fe-2af1-4b12-aa98-662fbf13510a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=954033746 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.954033746 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_128.3777144958
Short name	T200
Test name
Test status
Simulation time	51156055042 ps
CPU time	4357.48 seconds
Started	Jun 13 12:40:15 PM PDT 24
Finished	Jun 13 01:52:53 PM PDT 24
Peak memory	647000 kb
Host	smart-020aea83-953a-4ec9-b3de-0f4cb378848a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3777144958 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3777144958 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/41.kmac_test_vectors_shake_256.342201744
Short name	T1063
Test name
Test status
Simulation time	87418852499 ps
CPU time	3551.22 seconds
Started	Jun 13 12:40:15 PM PDT 24
Finished	Jun 13 01:39:26 PM PDT 24
Peak memory	551920 kb
Host	smart-1aa68fc1-191d-4fbd-8bd1-bcc44423ab79
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=342201744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.342201744 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/41.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/42.kmac_alert_test.2839771409
Short name	T451
Test name
Test status
Simulation time	102490906 ps
CPU time	0.76 seconds
Started	Jun 13 12:40:38 PM PDT 24
Finished	Jun 13 12:40:40 PM PDT 24
Peak memory	205232 kb
Host	smart-73c930ad-4cc4-4760-adf3-ada4b00d9845
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839771409 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2839771409 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_alert_test/latest

Test location	/workspace/coverage/default/42.kmac_app.1793081329
Short name	T1011
Test name
Test status
Simulation time	4970936077 ps
CPU time	225.74 seconds
Started	Jun 13 12:40:30 PM PDT 24
Finished	Jun 13 12:44:17 PM PDT 24
Peak memory	243580 kb
Host	smart-5481fcb0-1958-451e-b112-79527670f126
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1793081329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.1793081329 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_app/latest

Test location	/workspace/coverage/default/42.kmac_burst_write.3524519559
Short name	T915
Test name
Test status
Simulation time	136318724 ps
CPU time	1.36 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:40:25 PM PDT 24
Peak memory	217416 kb
Host	smart-08a29d58-89f3-495a-803c-2facf36d6934
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3524519559 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.3524519559 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_burst_write/latest

Test location	/workspace/coverage/default/42.kmac_entropy_refresh.2209750903
Short name	T728
Test name
Test status
Simulation time	2446212094 ps
CPU time	16.22 seconds
Started	Jun 13 12:40:32 PM PDT 24
Finished	Jun 13 12:40:49 PM PDT 24
Peak memory	219876 kb
Host	smart-e8dbb6f6-7a6e-44b5-bd13-cf21dbb62e87
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2209750903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2209750903 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/42.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/42.kmac_key_error.2715858664
Short name	T652
Test name
Test status
Simulation time	4199599356 ps
CPU time	7.17 seconds
Started	Jun 13 12:40:36 PM PDT 24
Finished	Jun 13 12:40:43 PM PDT 24
Peak memory	215728 kb
Host	smart-9ad1f7bc-9136-4c64-8065-3904beb51660
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715858664 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.2715858664 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_key_error/latest

Test location	/workspace/coverage/default/42.kmac_lc_escalation.3505592151
Short name	T1014
Test name
Test status
Simulation time	112350199 ps
CPU time	1.25 seconds
Started	Jun 13 12:40:39 PM PDT 24
Finished	Jun 13 12:40:41 PM PDT 24
Peak memory	215624 kb
Host	smart-a228ce68-d027-47ca-9f20-aedb85240d20
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3505592151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.3505592151 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/42.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/42.kmac_long_msg_and_output.2471836199
Short name	T582
Test name
Test status
Simulation time	108614654885 ps
CPU time	2268.7 seconds
Started	Jun 13 12:40:22 PM PDT 24
Finished	Jun 13 01:18:11 PM PDT 24
Peak memory	469948 kb
Host	smart-dfce0b3f-0337-4431-b220-fedbdd4c024c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471836199 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a nd_output.2471836199 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/42.kmac_sideload.809048153
Short name	T339
Test name
Test status
Simulation time	13246899080 ps
CPU time	108.53 seconds
Started	Jun 13 12:40:23 PM PDT 24
Finished	Jun 13 12:42:13 PM PDT 24
Peak memory	228120 kb
Host	smart-2871c240-924a-4744-9ee0-93fd52601843
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809048153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.809048153 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_sideload/latest

Test location	/workspace/coverage/default/42.kmac_smoke.3872071595
Short name	T274
Test name
Test status
Simulation time	1405683659 ps
CPU time	5.66 seconds
Started	Jun 13 12:40:22 PM PDT 24
Finished	Jun 13 12:40:28 PM PDT 24
Peak memory	215784 kb
Host	smart-45ccec5b-4c77-4df6-86b4-08745101a99f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872071595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.3872071595 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_smoke/latest

Test location	/workspace/coverage/default/42.kmac_stress_all.1415104985
Short name	T751
Test name
Test status
Simulation time	46489347747 ps
CPU time	336.6 seconds
Started	Jun 13 12:40:39 PM PDT 24
Finished	Jun 13 12:46:17 PM PDT 24
Peak memory	270588 kb
Host	smart-6d55c6a6-390c-4d21-a458-c327b785afa8
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1415104985 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.1415104985 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all/latest

Test location	/workspace/coverage/default/42.kmac_stress_all_with_rand_reset.2791293278
Short name	T738
Test name
Test status
Simulation time	108390869106 ps
CPU time	1019.23 seconds
Started	Jun 13 12:40:39 PM PDT 24
Finished	Jun 13 12:57:39 PM PDT 24
Peak memory	289436 kb
Host	smart-0304571f-6a9f-4a47-af27-799f3ecbcdb4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2791293278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all_with_rand_reset.2791293278 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac.971125277
Short name	T380
Test name
Test status
Simulation time	226523176 ps
CPU time	4.68 seconds
Started	Jun 13 12:40:32 PM PDT 24
Finished	Jun 13 12:40:37 PM PDT 24
Peak memory	215752 kb
Host	smart-abcf9c01-f1b5-4ddf-8bf6-f256e20c2f29
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971125277 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 42.kmac_test_vectors_kmac.971125277 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_kmac_xof.1383006541
Short name	T656
Test name
Test status
Simulation time	693605012 ps
CPU time	4.75 seconds
Started	Jun 13 12:40:32 PM PDT 24
Finished	Jun 13 12:40:38 PM PDT 24
Peak memory	215800 kb
Host	smart-3f0d3c24-670d-48a1-bdb6-86919e6e15dd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383006541 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_kmac_xof.1383006541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_224.86495427
Short name	T219
Test name
Test status
Simulation time	66662314734 ps
CPU time	1797.11 seconds
Started	Jun 13 12:40:24 PM PDT 24
Finished	Jun 13 01:10:21 PM PDT 24
Peak memory	396836 kb
Host	smart-e602b0d5-43fb-4691-9a18-b400a73903e1
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=86495427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.86495427 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_256.3003202540
Short name	T1045
Test name
Test status
Simulation time	832431700857 ps
CPU time	2111.8 seconds
Started	Jun 13 12:40:29 PM PDT 24
Finished	Jun 13 01:15:41 PM PDT 24
Peak memory	374836 kb
Host	smart-52f090fe-faf3-4174-8771-68f717b60773
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3003202540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3003202540 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_384.2896145024
Short name	T610
Test name
Test status
Simulation time	632251281542 ps
CPU time	1436.34 seconds
Started	Jun 13 12:40:30 PM PDT 24
Finished	Jun 13 01:04:27 PM PDT 24
Peak memory	332432 kb
Host	smart-fe383efa-d5c3-42fc-9683-815a447c7c54
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2896145024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.2896145024 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_sha3_512.1762859586
Short name	T651
Test name
Test status
Simulation time	32284611567 ps
CPU time	904.97 seconds
Started	Jun 13 12:40:31 PM PDT 24
Finished	Jun 13 12:55:36 PM PDT 24
Peak memory	293336 kb
Host	smart-6df04c93-a043-41b8-a69b-2be2c7d8a6e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1762859586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.1762859586 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_128.3180833984
Short name	T496
Test name
Test status
Simulation time	1025118278969 ps
CPU time	5241.24 seconds
Started	Jun 13 12:40:30 PM PDT 24
Finished	Jun 13 02:07:53 PM PDT 24
Peak memory	648608 kb
Host	smart-12d943e8-d412-4fcd-b6be-9935ceacbd79
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3180833984 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3180833984 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/42.kmac_test_vectors_shake_256.568396545
Short name	T407
Test name
Test status
Simulation time	90884132656 ps
CPU time	3475.3 seconds
Started	Jun 13 12:41:30 PM PDT 24
Finished	Jun 13 01:39:26 PM PDT 24
Peak memory	550664 kb
Host	smart-4a3cb63e-7d3a-4467-99f7-7a7edfefe567
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=568396545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.568396545 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/42.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/43.kmac_alert_test.2507531086
Short name	T1020
Test name
Test status
Simulation time	24151061 ps
CPU time	0.86 seconds
Started	Jun 13 12:40:54 PM PDT 24
Finished	Jun 13 12:40:55 PM PDT 24
Peak memory	205060 kb
Host	smart-015f8494-8a0f-4645-bf94-b9cb65b24e27
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507531086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.2507531086 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_alert_test/latest

Test location	/workspace/coverage/default/43.kmac_app.2338909541
Short name	T689
Test name
Test status
Simulation time	1947899556 ps
CPU time	43.88 seconds
Started	Jun 13 12:40:42 PM PDT 24
Finished	Jun 13 12:41:26 PM PDT 24
Peak memory	223864 kb
Host	smart-47df28f2-e0c0-4984-b364-5f5661b6effc
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2338909541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.2338909541 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_app/latest

Test location	/workspace/coverage/default/43.kmac_burst_write.2272221777
Short name	T801
Test name
Test status
Simulation time	30249333033 ps
CPU time	643.44 seconds
Started	Jun 13 12:40:38 PM PDT 24
Finished	Jun 13 12:51:22 PM PDT 24
Peak memory	231900 kb
Host	smart-9cc262f8-780c-4df2-b6e4-64f559086ac4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2272221777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.2272221777 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_burst_write/latest

Test location	/workspace/coverage/default/43.kmac_entropy_refresh.547550853
Short name	T997
Test name
Test status
Simulation time	50242368059 ps
CPU time	252.73 seconds
Started	Jun 13 12:40:44 PM PDT 24
Finished	Jun 13 12:44:57 PM PDT 24
Peak memory	245144 kb
Host	smart-170c4dff-94f9-4df5-ad6d-72319081577b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=547550853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.547550853 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/43.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/43.kmac_error.2931845164
Short name	T309
Test name
Test status
Simulation time	14880997118 ps
CPU time	362.75 seconds
Started	Jun 13 12:40:42 PM PDT 24
Finished	Jun 13 12:46:45 PM PDT 24
Peak memory	256800 kb
Host	smart-314b306a-7805-4ece-8339-768da94774a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931845164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2931845164 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_error/latest

Test location	/workspace/coverage/default/43.kmac_key_error.2878216248
Short name	T1066
Test name
Test status
Simulation time	692265113 ps
CPU time	4.92 seconds
Started	Jun 13 12:40:55 PM PDT 24
Finished	Jun 13 12:41:00 PM PDT 24
Peak memory	215568 kb
Host	smart-2b958451-8294-4f9f-a218-66b04f9ec928
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2878216248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2878216248 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_key_error/latest

Test location	/workspace/coverage/default/43.kmac_lc_escalation.2502136030
Short name	T257
Test name
Test status
Simulation time	62509739 ps
CPU time	1.23 seconds
Started	Jun 13 12:40:53 PM PDT 24
Finished	Jun 13 12:40:55 PM PDT 24
Peak memory	215652 kb
Host	smart-a7412bec-e5fd-46d8-8c4b-33d0e5f5ca7e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502136030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.2502136030 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/43.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/43.kmac_long_msg_and_output.2007551405
Short name	T239
Test name
Test status
Simulation time	112835472815 ps
CPU time	908.63 seconds
Started	Jun 13 12:40:38 PM PDT 24
Finished	Jun 13 12:55:47 PM PDT 24
Peak memory	300780 kb
Host	smart-e997a4ae-8e2b-4d97-8015-1da8b6468892
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007551405 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a nd_output.2007551405 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/43.kmac_sideload.804496060
Short name	T66
Test name
Test status
Simulation time	5714816484 ps
CPU time	134.11 seconds
Started	Jun 13 12:40:36 PM PDT 24
Finished	Jun 13 12:42:51 PM PDT 24
Peak memory	231692 kb
Host	smart-93cfd6c9-0bdc-4970-b8f1-0a02c117e0d7
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804496060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.804496060 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_sideload/latest

Test location	/workspace/coverage/default/43.kmac_smoke.1851469136
Short name	T586
Test name
Test status
Simulation time	3699552622 ps
CPU time	18.12 seconds
Started	Jun 13 12:40:38 PM PDT 24
Finished	Jun 13 12:40:57 PM PDT 24
Peak memory	224032 kb
Host	smart-9cab90ce-5445-4130-87a7-4d17c86c15ea
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851469136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1851469136 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_smoke/latest

Test location	/workspace/coverage/default/43.kmac_stress_all.3878022440
Short name	T362
Test name
Test status
Simulation time	41423910701 ps
CPU time	338.14 seconds
Started	Jun 13 12:40:54 PM PDT 24
Finished	Jun 13 12:46:32 PM PDT 24
Peak memory	289820 kb
Host	smart-98a20e55-ae63-4d2f-8ab4-2582d3e7b2dc
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3878022440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.3878022440 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_stress_all/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac.322396639
Short name	T680
Test name
Test status
Simulation time	179109566 ps
CPU time	4.95 seconds
Started	Jun 13 12:40:45 PM PDT 24
Finished	Jun 13 12:40:50 PM PDT 24
Peak memory	215836 kb
Host	smart-e4775cbf-37da-4a52-a9b1-7e3f7b74325f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322396639 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 43.kmac_test_vectors_kmac.322396639 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_kmac_xof.3165036217
Short name	T628
Test name
Test status
Simulation time	233109273 ps
CPU time	4.45 seconds
Started	Jun 13 12:40:44 PM PDT 24
Finished	Jun 13 12:40:49 PM PDT 24
Peak memory	215720 kb
Host	smart-8843e680-15e2-4ecf-94e6-d8510bfb1768
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165036217 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_kmac_xof.3165036217 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_224.419150545
Short name	T899
Test name
Test status
Simulation time	58238136309 ps
CPU time	1497.05 seconds
Started	Jun 13 12:40:43 PM PDT 24
Finished	Jun 13 01:05:41 PM PDT 24
Peak memory	387760 kb
Host	smart-5ab7077a-8436-4f91-9f42-5ac4c27c3166
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=419150545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.419150545 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_256.3155444486
Short name	T632
Test name
Test status
Simulation time	547316058658 ps
CPU time	1574.75 seconds
Started	Jun 13 12:40:43 PM PDT 24
Finished	Jun 13 01:06:58 PM PDT 24
Peak memory	368548 kb
Host	smart-0a1c0ded-b4b3-4f9d-a039-154b0f81183d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3155444486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.3155444486 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_384.1469510108
Short name	T212
Test name
Test status
Simulation time	197989163756 ps
CPU time	1355.88 seconds
Started	Jun 13 12:40:43 PM PDT 24
Finished	Jun 13 01:03:20 PM PDT 24
Peak memory	338360 kb
Host	smart-b3bda66d-8c06-4c37-b104-44b403e6faba
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1469510108 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.1469510108 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_sha3_512.256834642
Short name	T745
Test name
Test status
Simulation time	274561310056 ps
CPU time	946.05 seconds
Started	Jun 13 12:40:44 PM PDT 24
Finished	Jun 13 12:56:30 PM PDT 24
Peak memory	296364 kb
Host	smart-bb98cd45-d8c0-472f-9956-c60bc2df10cc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=256834642 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.256834642 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_128.1565283145
Short name	T684
Test name
Test status
Simulation time	686628175341 ps
CPU time	5080.92 seconds
Started	Jun 13 12:40:44 PM PDT 24
Finished	Jun 13 02:05:26 PM PDT 24
Peak memory	649412 kb
Host	smart-9e231755-ca08-4703-b084-c8d440928b16
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1565283145 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.1565283145 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/43.kmac_test_vectors_shake_256.2575629130
Short name	T475
Test name
Test status
Simulation time	43243211006 ps
CPU time	3287.14 seconds
Started	Jun 13 12:40:43 PM PDT 24
Finished	Jun 13 01:35:31 PM PDT 24
Peak memory	560864 kb
Host	smart-e0232d03-91bc-4f12-b45a-3b4f16ec4e5a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2575629130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.2575629130 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/43.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/44.kmac_alert_test.3688547953
Short name	T744
Test name
Test status
Simulation time	13840114 ps
CPU time	0.78 seconds
Started	Jun 13 12:41:26 PM PDT 24
Finished	Jun 13 12:41:28 PM PDT 24
Peak memory	205224 kb
Host	smart-d04b685b-69ac-4f15-88d5-31b7ccf39e78
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688547953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.3688547953 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_alert_test/latest

Test location	/workspace/coverage/default/44.kmac_app.1935060933
Short name	T700
Test name
Test status
Simulation time	21025246761 ps
CPU time	137.05 seconds
Started	Jun 13 12:41:25 PM PDT 24
Finished	Jun 13 12:43:42 PM PDT 24
Peak memory	232324 kb
Host	smart-1bed9d7a-4284-4800-a1c7-540a3868ddfb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1935060933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.1935060933 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_app/latest

Test location	/workspace/coverage/default/44.kmac_burst_write.3771347830
Short name	T584
Test name
Test status
Simulation time	104223935728 ps
CPU time	386.67 seconds
Started	Jun 13 12:40:53 PM PDT 24
Finished	Jun 13 12:47:20 PM PDT 24
Peak memory	228436 kb
Host	smart-ee8f29dd-ef00-45f3-b6ac-46cc1d7d5cd6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3771347830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.3771347830 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_burst_write/latest

Test location	/workspace/coverage/default/44.kmac_entropy_refresh.1628467169
Short name	T402
Test name
Test status
Simulation time	5312131089 ps
CPU time	160.26 seconds
Started	Jun 13 12:41:27 PM PDT 24
Finished	Jun 13 12:44:07 PM PDT 24
Peak memory	235976 kb
Host	smart-c48aaf7b-9a3c-4eb0-a7bf-08b6a1deb3c9
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1628467169 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.1628467169 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/44.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/44.kmac_error.1697782765
Short name	T1019
Test name
Test status
Simulation time	71632879341 ps
CPU time	392.45 seconds
Started	Jun 13 12:41:27 PM PDT 24
Finished	Jun 13 12:48:00 PM PDT 24
Peak memory	257576 kb
Host	smart-72d2b5e3-33b4-471e-84f2-2e58b798d553
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1697782765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1697782765 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_error/latest

Test location	/workspace/coverage/default/44.kmac_key_error.3700921975
Short name	T21
Test name
Test status
Simulation time	4856898747 ps
CPU time	7.04 seconds
Started	Jun 13 12:41:26 PM PDT 24
Finished	Jun 13 12:41:33 PM PDT 24
Peak memory	207428 kb
Host	smart-56a26b6f-a0a0-49b5-8e2f-2a33741b8bf3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3700921975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.3700921975 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_key_error/latest

Test location	/workspace/coverage/default/44.kmac_lc_escalation.1853960264
Short name	T78
Test name
Test status
Simulation time	39079831 ps
CPU time	1.24 seconds
Started	Jun 13 12:41:27 PM PDT 24
Finished	Jun 13 12:41:29 PM PDT 24
Peak memory	215700 kb
Host	smart-24f74e7a-2c4d-413d-bd6f-a4033fde958b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1853960264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.1853960264 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/44.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/44.kmac_long_msg_and_output.2361065376
Short name	T495
Test name
Test status
Simulation time	1530204225671 ps
CPU time	2624.21 seconds
Started	Jun 13 12:40:53 PM PDT 24
Finished	Jun 13 01:24:38 PM PDT 24
Peak memory	435344 kb
Host	smart-2cad5b82-a922-4388-8d91-b128ba21008c
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361065376 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a nd_output.2361065376 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/44.kmac_sideload.4168478352
Short name	T1077
Test name
Test status
Simulation time	4522062853 ps
CPU time	365.5 seconds
Started	Jun 13 12:40:53 PM PDT 24
Finished	Jun 13 12:46:59 PM PDT 24
Peak memory	246636 kb
Host	smart-925f223d-6235-445c-9531-fc2acbf64064
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168478352 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload.4168478352 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_sideload/latest

Test location	/workspace/coverage/default/44.kmac_smoke.4009332243
Short name	T655
Test name
Test status
Simulation time	28795373 ps
CPU time	1.57 seconds
Started	Jun 13 12:40:54 PM PDT 24
Finished	Jun 13 12:40:56 PM PDT 24
Peak memory	221112 kb
Host	smart-384b1851-2d49-4061-9242-6fbd3ce49e23
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4009332243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_smoke.4009332243 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_smoke/latest

Test location	/workspace/coverage/default/44.kmac_stress_all.411791156
Short name	T51
Test name
Test status
Simulation time	150931666453 ps
CPU time	1065.48 seconds
Started	Jun 13 12:41:26 PM PDT 24
Finished	Jun 13 12:59:12 PM PDT 24
Peak memory	355396 kb
Host	smart-834382f6-7b4c-4c0b-bf58-6bff60303fce
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=411791156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.411791156 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_stress_all/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac.547354670
Short name	T306
Test name
Test status
Simulation time	589625464 ps
CPU time	4.46 seconds
Started	Jun 13 12:41:25 PM PDT 24
Finished	Jun 13 12:41:30 PM PDT 24
Peak memory	215768 kb
Host	smart-10d80214-9fda-4c20-9af4-55723b063ee4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547354670 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 44.kmac_test_vectors_kmac.547354670 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_kmac_xof.3515270040
Short name	T465
Test name
Test status
Simulation time	355132077 ps
CPU time	3.99 seconds
Started	Jun 13 12:41:28 PM PDT 24
Finished	Jun 13 12:41:32 PM PDT 24
Peak memory	215804 kb
Host	smart-e3282af9-de69-40a6-bd22-5a4d7c5df97d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515270040 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_kmac_xof.3515270040 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_224.3904005920
Short name	T667
Test name
Test status
Simulation time	19478521321 ps
CPU time	1592.21 seconds
Started	Jun 13 12:40:54 PM PDT 24
Finished	Jun 13 01:07:27 PM PDT 24
Peak memory	389308 kb
Host	smart-7521f237-1a2d-4353-8f15-c46c669592c0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3904005920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.3904005920 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_256.2690469055
Short name	T1032
Test name
Test status
Simulation time	26651950280 ps
CPU time	1481.63 seconds
Started	Jun 13 12:41:25 PM PDT 24
Finished	Jun 13 01:06:07 PM PDT 24
Peak memory	371412 kb
Host	smart-24480e86-2ed1-423e-ad77-617535a0c0fd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2690469055 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2690469055 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_384.120517490
Short name	T284
Test name
Test status
Simulation time	159499882480 ps
CPU time	1390.13 seconds
Started	Jun 13 12:41:23 PM PDT 24
Finished	Jun 13 01:04:34 PM PDT 24
Peak memory	334936 kb
Host	smart-30163230-2ff1-4b50-9218-c21849a9f885
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=120517490 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.120517490 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_sha3_512.4087874320
Short name	T386
Test name
Test status
Simulation time	202209852899 ps
CPU time	997.62 seconds
Started	Jun 13 12:41:24 PM PDT 24
Finished	Jun 13 12:58:02 PM PDT 24
Peak memory	293924 kb
Host	smart-eacfd754-4f86-47de-864d-540c33138c5c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4087874320 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.4087874320 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_128.1107843510
Short name	T825
Test name
Test status
Simulation time	2479307042205 ps
CPU time	4860.58 seconds
Started	Jun 13 12:41:25 PM PDT 24
Finished	Jun 13 02:02:27 PM PDT 24
Peak memory	650988 kb
Host	smart-bc2425ef-00e0-496f-b0b9-7127318596fb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1107843510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1107843510 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/44.kmac_test_vectors_shake_256.1478753519
Short name	T675
Test name
Test status
Simulation time	1444486180264 ps
CPU time	5038.71 seconds
Started	Jun 13 12:41:25 PM PDT 24
Finished	Jun 13 02:05:25 PM PDT 24
Peak memory	561360 kb
Host	smart-88ad2a9e-b869-4aef-bec5-1baf4ad49690
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1478753519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.1478753519 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/44.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/45.kmac_alert_test.1884557545
Short name	T860
Test name
Test status
Simulation time	20619325 ps
CPU time	0.86 seconds
Started	Jun 13 12:41:34 PM PDT 24
Finished	Jun 13 12:41:35 PM PDT 24
Peak memory	205232 kb
Host	smart-a242a792-041f-41e7-8c7b-d0a7df3e6d5e
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884557545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.1884557545 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_alert_test/latest

Test location	/workspace/coverage/default/45.kmac_app.2879300812
Short name	T95
Test name
Test status
Simulation time	148657968068 ps
CPU time	163.62 seconds
Started	Jun 13 12:41:36 PM PDT 24
Finished	Jun 13 12:44:20 PM PDT 24
Peak memory	235952 kb
Host	smart-3c55f651-0c9f-44c8-9554-f4ef2fea324b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2879300812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.2879300812 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_app/latest

Test location	/workspace/coverage/default/45.kmac_burst_write.1498579807
Short name	T907
Test name
Test status
Simulation time	24682846309 ps
CPU time	148.48 seconds
Started	Jun 13 12:41:31 PM PDT 24
Finished	Jun 13 12:44:00 PM PDT 24
Peak memory	223196 kb
Host	smart-c3cc1c1f-2598-46a6-b088-e1e615c17f59
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1498579807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.1498579807 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_burst_write/latest

Test location	/workspace/coverage/default/45.kmac_entropy_refresh.1483065044
Short name	T974
Test name
Test status
Simulation time	7579291231 ps
CPU time	42.18 seconds
Started	Jun 13 12:41:33 PM PDT 24
Finished	Jun 13 12:42:16 PM PDT 24
Peak memory	223904 kb
Host	smart-e3c9fe8a-6476-4bf4-8d03-55717a810a50
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483065044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_entropy_refresh.1483065044 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/45.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/45.kmac_error.4068788700
Short name	T29
Test name
Test status
Simulation time	2263242180 ps
CPU time	180.54 seconds
Started	Jun 13 12:41:32 PM PDT 24
Finished	Jun 13 12:44:33 PM PDT 24
Peak memory	240500 kb
Host	smart-d02f9545-c0b2-47fd-976a-f9fe0d2b6415
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4068788700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.4068788700 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_error/latest

Test location	/workspace/coverage/default/45.kmac_key_error.954478758
Short name	T549
Test name
Test status
Simulation time	3310306710 ps
CPU time	8.92 seconds
Started	Jun 13 12:41:35 PM PDT 24
Finished	Jun 13 12:41:44 PM PDT 24
Peak memory	207508 kb
Host	smart-f44f4372-e2ab-407f-93f8-a0d08baa38fb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954478758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.954478758 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_key_error/latest

Test location	/workspace/coverage/default/45.kmac_lc_escalation.2752607253
Short name	T431
Test name
Test status
Simulation time	23314580 ps
CPU time	1.15 seconds
Started	Jun 13 12:41:34 PM PDT 24
Finished	Jun 13 12:41:36 PM PDT 24
Peak memory	215624 kb
Host	smart-650c3485-8a7d-4dbd-8db3-bf358e6f69c0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2752607253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.2752607253 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/45.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/45.kmac_long_msg_and_output.3000255741
Short name	T1061
Test name
Test status
Simulation time	23496256268 ps
CPU time	993.83 seconds
Started	Jun 13 12:41:33 PM PDT 24
Finished	Jun 13 12:58:07 PM PDT 24
Peak memory	326592 kb
Host	smart-f5b081e5-2c0c-4112-a09d-086e7ad2dea2
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000255741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a nd_output.3000255741 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/45.kmac_sideload.3294694884
Short name	T1085
Test name
Test status
Simulation time	29827270427 ps
CPU time	81.14 seconds
Started	Jun 13 12:41:31 PM PDT 24
Finished	Jun 13 12:42:53 PM PDT 24
Peak memory	224816 kb
Host	smart-4fe29143-5891-4cc4-95af-df048ec22530
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294694884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3294694884 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_sideload/latest

Test location	/workspace/coverage/default/45.kmac_smoke.3712637340
Short name	T265
Test name
Test status
Simulation time	2527707515 ps
CPU time	31.8 seconds
Started	Jun 13 12:41:31 PM PDT 24
Finished	Jun 13 12:42:03 PM PDT 24
Peak memory	219056 kb
Host	smart-7d9a4d7b-ba91-4d72-a3ba-bb3afb2d3c75
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3712637340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.3712637340 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_smoke/latest

Test location	/workspace/coverage/default/45.kmac_stress_all.1489680223
Short name	T879
Test name
Test status
Simulation time	9616744418 ps
CPU time	192.46 seconds
Started	Jun 13 12:41:35 PM PDT 24
Finished	Jun 13 12:44:47 PM PDT 24
Peak memory	237292 kb
Host	smart-b0598bc3-f461-48c8-8e42-1f7159c9726f
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1489680223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.1489680223 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all/latest

Test location	/workspace/coverage/default/45.kmac_stress_all_with_rand_reset.3516836533
Short name	T31
Test name
Test status
Simulation time	18474846702 ps
CPU time	943.07 seconds
Started	Jun 13 12:41:32 PM PDT 24
Finished	Jun 13 12:57:16 PM PDT 24
Peak memory	332600 kb
Host	smart-a49a19a3-0dc5-4096-8af5-cd281191963a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3516836533 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all_with_rand_reset.3516836533 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac.4008075966
Short name	T396
Test name
Test status
Simulation time	66215766 ps
CPU time	4.39 seconds
Started	Jun 13 12:41:36 PM PDT 24
Finished	Jun 13 12:41:41 PM PDT 24
Peak memory	215792 kb
Host	smart-af79b632-5b76-4438-8519-72162162bec7
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008075966 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 45.kmac_test_vectors_kmac.4008075966 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_kmac_xof.57577929
Short name	T1069
Test name
Test status
Simulation time	490294323 ps
CPU time	5.18 seconds
Started	Jun 13 12:41:33 PM PDT 24
Finished	Jun 13 12:41:39 PM PDT 24
Peak memory	215820 kb
Host	smart-559bc364-bfb2-4cc6-a0a2-7706b76c9939
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57577929 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 45.kmac_test_vectors_kmac_xof.57577929 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_224.2656886741
Short name	T347
Test name
Test status
Simulation time	19619099159 ps
CPU time	1529.83 seconds
Started	Jun 13 12:41:30 PM PDT 24
Finished	Jun 13 01:07:01 PM PDT 24
Peak memory	377164 kb
Host	smart-4cc33817-cd98-4ef5-9e68-a1a98a151b5c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2656886741 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2656886741 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_256.672627299
Short name	T238
Test name
Test status
Simulation time	18516689001 ps
CPU time	1466.22 seconds
Started	Jun 13 12:41:30 PM PDT 24
Finished	Jun 13 01:05:57 PM PDT 24
Peak memory	393252 kb
Host	smart-5d2e531e-09e5-41fa-8695-76750f59c7eb
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=672627299 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.672627299 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_384.911826628
Short name	T393
Test name
Test status
Simulation time	48308468652 ps
CPU time	1253.84 seconds
Started	Jun 13 12:41:31 PM PDT 24
Finished	Jun 13 01:02:25 PM PDT 24
Peak memory	331876 kb
Host	smart-09b6c484-085c-48cf-a285-869ae64bf350
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=911826628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.911826628 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_sha3_512.3900773920
Short name	T764
Test name
Test status
Simulation time	65426441972 ps
CPU time	898.34 seconds
Started	Jun 13 12:41:32 PM PDT 24
Finished	Jun 13 12:56:31 PM PDT 24
Peak memory	291236 kb
Host	smart-bfc34977-5a5a-441d-8303-5a230a87af92
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3900773920 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.3900773920 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_128.941458277
Short name	T181
Test name
Test status
Simulation time	494077455492 ps
CPU time	4599.25 seconds
Started	Jun 13 12:41:32 PM PDT 24
Finished	Jun 13 01:58:13 PM PDT 24
Peak memory	656612 kb
Host	smart-0c441d31-cd8f-4ca3-867f-fadc48a2fe60
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=941458277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.941458277 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/45.kmac_test_vectors_shake_256.3428661229
Short name	T846
Test name
Test status
Simulation time	144373535528 ps
CPU time	3787.7 seconds
Started	Jun 13 12:41:31 PM PDT 24
Finished	Jun 13 01:44:39 PM PDT 24
Peak memory	555128 kb
Host	smart-d5eaa583-7494-49b3-b341-d2278a888563
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3428661229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.3428661229 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/45.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/46.kmac_alert_test.4231608181
Short name	T245
Test name
Test status
Simulation time	15587886 ps
CPU time	0.78 seconds
Started	Jun 13 12:41:42 PM PDT 24
Finished	Jun 13 12:41:43 PM PDT 24
Peak memory	205228 kb
Host	smart-8a1b1135-87ce-4662-b41a-2d327094f890
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231608181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.4231608181 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_alert_test/latest

Test location	/workspace/coverage/default/46.kmac_app.2572695566
Short name	T857
Test name
Test status
Simulation time	1370613336 ps
CPU time	58.57 seconds
Started	Jun 13 12:41:41 PM PDT 24
Finished	Jun 13 12:42:40 PM PDT 24
Peak memory	224308 kb
Host	smart-d661d3d1-4eab-45c0-abb0-1cb9c2d9cd67
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572695566 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2572695566 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_app/latest

Test location	/workspace/coverage/default/46.kmac_burst_write.4055930408
Short name	T326
Test name
Test status
Simulation time	17419174607 ps
CPU time	109.45 seconds
Started	Jun 13 12:41:39 PM PDT 24
Finished	Jun 13 12:43:28 PM PDT 24
Peak memory	237772 kb
Host	smart-25b55c11-f570-421b-840d-1c1ea225da51
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4055930408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.4055930408 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_burst_write/latest

Test location	/workspace/coverage/default/46.kmac_entropy_refresh.3986813023
Short name	T967
Test name
Test status
Simulation time	4216854036 ps
CPU time	23.91 seconds
Started	Jun 13 12:41:40 PM PDT 24
Finished	Jun 13 12:42:04 PM PDT 24
Peak memory	220168 kb
Host	smart-a122808a-3a22-45e8-9de2-a154c6afc28b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3986813023 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3986813023 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/46.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/46.kmac_error.159128048
Short name	T335
Test name
Test status
Simulation time	49131078709 ps
CPU time	325.81 seconds
Started	Jun 13 12:41:42 PM PDT 24
Finished	Jun 13 12:47:08 PM PDT 24
Peak memory	256828 kb
Host	smart-605ce95d-5e6f-49ba-9d6f-4357b03814cf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159128048 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.159128048 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_error/latest

Test location	/workspace/coverage/default/46.kmac_key_error.3233420410
Short name	T883
Test name
Test status
Simulation time	8418835774 ps
CPU time	10.79 seconds
Started	Jun 13 12:41:39 PM PDT 24
Finished	Jun 13 12:41:50 PM PDT 24
Peak memory	207572 kb
Host	smart-eb919891-7598-4277-b459-3dae9dcffef1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3233420410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.3233420410 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_key_error/latest

Test location	/workspace/coverage/default/46.kmac_lc_escalation.3126054507
Short name	T34
Test name
Test status
Simulation time	98773105 ps
CPU time	1.42 seconds
Started	Jun 13 12:41:43 PM PDT 24
Finished	Jun 13 12:41:45 PM PDT 24
Peak memory	215524 kb
Host	smart-cb3b70fe-02c4-42fb-96dc-b6c04a426745
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3126054507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.3126054507 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/46.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/46.kmac_long_msg_and_output.3908935894
Short name	T572
Test name
Test status
Simulation time	84039831158 ps
CPU time	734.38 seconds
Started	Jun 13 12:41:36 PM PDT 24
Finished	Jun 13 12:53:51 PM PDT 24
Peak memory	287976 kb
Host	smart-03a9e5f1-092a-429f-8b1e-d437a567eaef
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908935894 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a nd_output.3908935894 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/46.kmac_sideload.3427014522
Short name	T759
Test name
Test status
Simulation time	31548145170 ps
CPU time	172.42 seconds
Started	Jun 13 12:41:36 PM PDT 24
Finished	Jun 13 12:44:29 PM PDT 24
Peak memory	232380 kb
Host	smart-dc7b1425-e5c6-4880-8b56-7754c06c6df4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427014522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.3427014522 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_sideload/latest

Test location	/workspace/coverage/default/46.kmac_smoke.363702100
Short name	T663
Test name
Test status
Simulation time	1591788312 ps
CPU time	13.67 seconds
Started	Jun 13 12:41:35 PM PDT 24
Finished	Jun 13 12:41:49 PM PDT 24
Peak memory	220648 kb
Host	smart-c8530b4c-d380-4779-9c2e-3dcc4ca9e44c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=363702100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.363702100 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_smoke/latest

Test location	/workspace/coverage/default/46.kmac_stress_all.695835697
Short name	T1075
Test name
Test status
Simulation time	42760151529 ps
CPU time	1712.95 seconds
Started	Jun 13 12:41:42 PM PDT 24
Finished	Jun 13 01:10:15 PM PDT 24
Peak memory	436636 kb
Host	smart-ad74c157-20b0-4db6-8fdb-6810c690a501
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=695835697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.695835697 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_stress_all/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac.4161003055
Short name	T540
Test name
Test status
Simulation time	2228797989 ps
CPU time	6.03 seconds
Started	Jun 13 12:41:43 PM PDT 24
Finished	Jun 13 12:41:49 PM PDT 24
Peak memory	215836 kb
Host	smart-073347c3-c702-4a58-aace-3127f97afd38
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161003055 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 46.kmac_test_vectors_kmac.4161003055 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_kmac_xof.98684280
Short name	T919
Test name
Test status
Simulation time	648319200 ps
CPU time	4.67 seconds
Started	Jun 13 12:41:42 PM PDT 24
Finished	Jun 13 12:41:47 PM PDT 24
Peak memory	215740 kb
Host	smart-8d295f05-2417-4af9-8a96-1ac226b9685d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98684280 -assert nopostproc +UVM_TESTNAME=kmac_base_t est +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 46.kmac_test_vectors_kmac_xof.98684280 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_224.3870565301
Short name	T1036
Test name
Test status
Simulation time	64449187843 ps
CPU time	1851.66 seconds
Started	Jun 13 12:41:40 PM PDT 24
Finished	Jun 13 01:12:33 PM PDT 24
Peak memory	389504 kb
Host	smart-3117a80f-3659-454d-a5b7-c0c752b25e6c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3870565301 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.3870565301 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_256.1520664412
Short name	T298
Test name
Test status
Simulation time	90781323230 ps
CPU time	1733.97 seconds
Started	Jun 13 12:41:37 PM PDT 24
Finished	Jun 13 01:10:31 PM PDT 24
Peak memory	371384 kb
Host	smart-a2e8efe9-194a-45f0-a1f1-1603ae74210d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1520664412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.1520664412 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_384.1318518242
Short name	T724
Test name
Test status
Simulation time	120831732992 ps
CPU time	1192.03 seconds
Started	Jun 13 12:41:37 PM PDT 24
Finished	Jun 13 01:01:29 PM PDT 24
Peak memory	329556 kb
Host	smart-d7119f16-ec67-44ec-a925-d028d0c472d5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1318518242 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.1318518242 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_sha3_512.734192507
Short name	T301
Test name
Test status
Simulation time	68258030426 ps
CPU time	927.83 seconds
Started	Jun 13 12:41:38 PM PDT 24
Finished	Jun 13 12:57:06 PM PDT 24
Peak memory	293980 kb
Host	smart-87654245-b06b-4189-a94e-8c2d49757062
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=734192507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.734192507 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_128.1462633873
Short name	T635
Test name
Test status
Simulation time	181989302496 ps
CPU time	4997.33 seconds
Started	Jun 13 12:41:37 PM PDT 24
Finished	Jun 13 02:04:55 PM PDT 24
Peak memory	645120 kb
Host	smart-03eecfea-777b-4131-a057-6f9192de01a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1462633873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1462633873 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/46.kmac_test_vectors_shake_256.3559403051
Short name	T313
Test name
Test status
Simulation time	772482056824 ps
CPU time	4027.16 seconds
Started	Jun 13 12:41:40 PM PDT 24
Finished	Jun 13 01:48:48 PM PDT 24
Peak memory	570316 kb
Host	smart-c147f76f-6544-4291-8381-64a5f5bbfbbd
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3559403051 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.3559403051 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/46.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/47.kmac_alert_test.3999394111
Short name	T272
Test name
Test status
Simulation time	39840927 ps
CPU time	0.82 seconds
Started	Jun 13 12:41:55 PM PDT 24
Finished	Jun 13 12:41:56 PM PDT 24
Peak memory	205236 kb
Host	smart-340a21e0-6687-4327-bee6-46ebfdd3c9cd
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999394111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.3999394111 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_alert_test/latest

Test location	/workspace/coverage/default/47.kmac_app.3730016861
Short name	T725
Test name
Test status
Simulation time	31988238668 ps
CPU time	202.96 seconds
Started	Jun 13 12:41:46 PM PDT 24
Finished	Jun 13 12:45:10 PM PDT 24
Peak memory	239656 kb
Host	smart-0c145a7d-794a-47cc-bcdf-3eccd622af24
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3730016861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.3730016861 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_app/latest

Test location	/workspace/coverage/default/47.kmac_burst_write.3093902388
Short name	T368
Test name
Test status
Simulation time	19105639121 ps
CPU time	145.44 seconds
Started	Jun 13 12:41:46 PM PDT 24
Finished	Jun 13 12:44:12 PM PDT 24
Peak memory	223292 kb
Host	smart-cda9cb2f-ed5d-4246-a465-4abd78f98bcb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093902388 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.3093902388 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_burst_write/latest

Test location	/workspace/coverage/default/47.kmac_entropy_refresh.854003316
Short name	T788
Test name
Test status
Simulation time	187244887062 ps
CPU time	343.25 seconds
Started	Jun 13 12:41:51 PM PDT 24
Finished	Jun 13 12:47:34 PM PDT 24
Peak memory	242584 kb
Host	smart-f75b6508-4fa3-476e-9770-14c5b5de30b2
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=854003316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.854003316 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/47.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/47.kmac_error.1341068240
Short name	T559
Test name
Test status
Simulation time	8598425739 ps
CPU time	121.5 seconds
Started	Jun 13 12:41:49 PM PDT 24
Finished	Jun 13 12:43:51 PM PDT 24
Peak memory	240352 kb
Host	smart-8670b36d-4662-4482-925c-766a68f9b90e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1341068240 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.1341068240 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_error/latest

Test location	/workspace/coverage/default/47.kmac_key_error.3654826594
Short name	T1001
Test name
Test status
Simulation time	2228850010 ps
CPU time	4.05 seconds
Started	Jun 13 12:41:53 PM PDT 24
Finished	Jun 13 12:41:57 PM PDT 24
Peak memory	207508 kb
Host	smart-15072e8b-7f1d-4bcc-b91a-cf1e09d7156b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3654826594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.3654826594 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_key_error/latest

Test location	/workspace/coverage/default/47.kmac_long_msg_and_output.1542336218
Short name	T880
Test name
Test status
Simulation time	98487534545 ps
CPU time	2216.02 seconds
Started	Jun 13 12:41:43 PM PDT 24
Finished	Jun 13 01:18:40 PM PDT 24
Peak memory	442056 kb
Host	smart-e8c6fbb0-cabe-400e-9f1a-190cf43a11d9
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542336218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_a nd_output.1542336218 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/47.kmac_sideload.2360320562
Short name	T835
Test name
Test status
Simulation time	592061331 ps
CPU time	48.67 seconds
Started	Jun 13 12:41:41 PM PDT 24
Finished	Jun 13 12:42:30 PM PDT 24
Peak memory	222268 kb
Host	smart-eb23d086-77ca-4f8d-ba2d-63d0c37920b6
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360320562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.2360320562 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_sideload/latest

Test location	/workspace/coverage/default/47.kmac_smoke.1464047373
Short name	T506
Test name
Test status
Simulation time	676556846 ps
CPU time	34.58 seconds
Started	Jun 13 12:41:41 PM PDT 24
Finished	Jun 13 12:42:16 PM PDT 24
Peak memory	216812 kb
Host	smart-5e935f9b-602a-4589-a5a0-2a78c706ed11
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1464047373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.1464047373 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_smoke/latest

Test location	/workspace/coverage/default/47.kmac_stress_all.1573294008
Short name	T26
Test name
Test status
Simulation time	20231370684 ps
CPU time	748.9 seconds
Started	Jun 13 12:41:47 PM PDT 24
Finished	Jun 13 12:54:16 PM PDT 24
Peak memory	348680 kb
Host	smart-c15a9eda-382f-4f28-8aab-a5c3f3b78eee
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1573294008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.1573294008 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_stress_all/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac.4102933012
Short name	T983
Test name
Test status
Simulation time	266615496 ps
CPU time	4.02 seconds
Started	Jun 13 12:41:46 PM PDT 24
Finished	Jun 13 12:41:50 PM PDT 24
Peak memory	215812 kb
Host	smart-2601cce0-8b3e-46ba-95dc-46ad48a33304
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102933012 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 47.kmac_test_vectors_kmac.4102933012 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3360639702
Short name	T457
Test name
Test status
Simulation time	167372497 ps
CPU time	3.75 seconds
Started	Jun 13 12:41:47 PM PDT 24
Finished	Jun 13 12:41:51 PM PDT 24
Peak memory	215776 kb
Host	smart-83a3852e-8f24-47f2-a5a0-4b0e29f6f670
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360639702 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3360639702 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_224.697444426
Short name	T937
Test name
Test status
Simulation time	85173757968 ps
CPU time	1764.76 seconds
Started	Jun 13 12:41:44 PM PDT 24
Finished	Jun 13 01:11:09 PM PDT 24
Peak memory	370332 kb
Host	smart-6757df8f-5d7c-4d32-9add-17c93da06dda
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=697444426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.697444426 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_256.666964124
Short name	T944
Test name
Test status
Simulation time	18104924786 ps
CPU time	1499.68 seconds
Started	Jun 13 12:41:43 PM PDT 24
Finished	Jun 13 01:06:43 PM PDT 24
Peak memory	388748 kb
Host	smart-09b87e69-f3cb-4363-be3a-c4e293c46525
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=666964124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.666964124 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_384.2830071498
Short name	T933
Test name
Test status
Simulation time	97553850410 ps
CPU time	1125.54 seconds
Started	Jun 13 12:41:43 PM PDT 24
Finished	Jun 13 01:00:29 PM PDT 24
Peak memory	335404 kb
Host	smart-3e4e2feb-b9bd-4a52-8abb-5f693f2a900a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2830071498 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.2830071498 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_sha3_512.2649884081
Short name	T505
Test name
Test status
Simulation time	9534569635 ps
CPU time	701.24 seconds
Started	Jun 13 12:41:42 PM PDT 24
Finished	Jun 13 12:53:24 PM PDT 24
Peak memory	295608 kb
Host	smart-ab7c8772-5354-4e8c-9f1f-1db3c4d45a4e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2649884081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.2649884081 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_128.2018406081
Short name	T804
Test name
Test status
Simulation time	263182424896 ps
CPU time	4925.94 seconds
Started	Jun 13 12:41:47 PM PDT 24
Finished	Jun 13 02:03:54 PM PDT 24
Peak memory	645068 kb
Host	smart-c0d8e875-3805-42ec-a333-2871cd947198
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2018406081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.2018406081 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/47.kmac_test_vectors_shake_256.788271935
Short name	T758
Test name
Test status
Simulation time	297636636794 ps
CPU time	4012.97 seconds
Started	Jun 13 12:41:46 PM PDT 24
Finished	Jun 13 01:48:40 PM PDT 24
Peak memory	547316 kb
Host	smart-5805cccb-7dd4-46ba-a1f9-6647ee7c91ad
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=788271935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.788271935 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/47.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/48.kmac_alert_test.2587794997
Short name	T775
Test name
Test status
Simulation time	17298855 ps
CPU time	0.8 seconds
Started	Jun 13 12:42:11 PM PDT 24
Finished	Jun 13 12:42:12 PM PDT 24
Peak memory	205268 kb
Host	smart-356f0209-2791-4089-8397-9882f7170489
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587794997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.2587794997 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_alert_test/latest

Test location	/workspace/coverage/default/48.kmac_app.1009187070
Short name	T1024
Test name
Test status
Simulation time	5464027977 ps
CPU time	231.08 seconds
Started	Jun 13 12:42:06 PM PDT 24
Finished	Jun 13 12:45:57 PM PDT 24
Peak memory	243740 kb
Host	smart-0a4e10c8-8493-4479-8c00-2d50aa2e953a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009187070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1009187070 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_app/latest

Test location	/workspace/coverage/default/48.kmac_burst_write.2127948660
Short name	T464
Test name
Test status
Simulation time	3255429155 ps
CPU time	292.23 seconds
Started	Jun 13 12:41:53 PM PDT 24
Finished	Jun 13 12:46:46 PM PDT 24
Peak memory	226776 kb
Host	smart-d016730a-dae8-4061-aecc-3c974da94752
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2127948660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.2127948660 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_burst_write/latest

Test location	/workspace/coverage/default/48.kmac_entropy_refresh.2780170733
Short name	T374
Test name
Test status
Simulation time	14417587666 ps
CPU time	223.58 seconds
Started	Jun 13 12:42:06 PM PDT 24
Finished	Jun 13 12:45:49 PM PDT 24
Peak memory	238456 kb
Host	smart-31bc23b3-a36f-4061-8e5f-76db5b9bad79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2780170733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.2780170733 +enable_masking=0 + sw_key_masked=0
Directory	/workspace/48.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/48.kmac_error.2118991523
Short name	T488
Test name
Test status
Simulation time	18491079393 ps
CPU time	373.84 seconds
Started	Jun 13 12:42:11 PM PDT 24
Finished	Jun 13 12:48:25 PM PDT 24
Peak memory	256760 kb
Host	smart-18bbaa84-7245-48bc-91f4-c0caefc832da
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2118991523 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.2118991523 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_error/latest

Test location	/workspace/coverage/default/48.kmac_key_error.3898050772
Short name	T61
Test name
Test status
Simulation time	932614499 ps
CPU time	2.89 seconds
Started	Jun 13 12:42:10 PM PDT 24
Finished	Jun 13 12:42:13 PM PDT 24
Peak memory	215660 kb
Host	smart-02b6898f-9b6d-43ed-9be2-022fbde3e905
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898050772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.3898050772 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_key_error/latest

Test location	/workspace/coverage/default/48.kmac_lc_escalation.3944605888
Short name	T376
Test name
Test status
Simulation time	194273887 ps
CPU time	1.48 seconds
Started	Jun 13 12:42:10 PM PDT 24
Finished	Jun 13 12:42:12 PM PDT 24
Peak memory	215596 kb
Host	smart-be4f4642-a5cc-45bd-9f57-c68f63c69e93
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3944605888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3944605888 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/48.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/48.kmac_long_msg_and_output.3537684102
Short name	T448
Test name
Test status
Simulation time	177725673476 ps
CPU time	1311.22 seconds
Started	Jun 13 12:41:55 PM PDT 24
Finished	Jun 13 01:03:47 PM PDT 24
Peak memory	348908 kb
Host	smart-d9ceea1b-c303-45e7-8afe-464db901f75a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537684102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a nd_output.3537684102 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/48.kmac_sideload.1235893963
Short name	T458
Test name
Test status
Simulation time	3659143024 ps
CPU time	271.27 seconds
Started	Jun 13 12:41:52 PM PDT 24
Finished	Jun 13 12:46:24 PM PDT 24
Peak memory	246016 kb
Host	smart-7d2b30fa-66a6-4bea-b097-8154f5c3067b
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235893963 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.1235893963 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_sideload/latest

Test location	/workspace/coverage/default/48.kmac_smoke.3540279485
Short name	T970
Test name
Test status
Simulation time	1540188863 ps
CPU time	20.19 seconds
Started	Jun 13 12:41:55 PM PDT 24
Finished	Jun 13 12:42:16 PM PDT 24
Peak memory	215992 kb
Host	smart-76097163-e4dc-41cf-a206-cc338d61d780
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3540279485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.3540279485 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_smoke/latest

Test location	/workspace/coverage/default/48.kmac_stress_all.1852225901
Short name	T568
Test name
Test status
Simulation time	6264434363 ps
CPU time	478.65 seconds
Started	Jun 13 12:42:10 PM PDT 24
Finished	Jun 13 12:50:10 PM PDT 24
Peak memory	300220 kb
Host	smart-6ea39713-d390-423a-89ff-526206119a46
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1852225901 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1852225901 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all/latest

Test location	/workspace/coverage/default/48.kmac_stress_all_with_rand_reset.995221431
Short name	T573
Test name
Test status
Simulation time	21151172918 ps
CPU time	1323.07 seconds
Started	Jun 13 12:42:12 PM PDT 24
Finished	Jun 13 01:04:15 PM PDT 24
Peak memory	350436 kb
Host	smart-5fa7a920-aaf1-4580-a566-a89417c14c4a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000 0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=995221431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all_with_rand_reset.995221431 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_stress_all_with_rand_reset/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac.2258614865
Short name	T781
Test name
Test status
Simulation time	334879915 ps
CPU time	4.5 seconds
Started	Jun 13 12:42:06 PM PDT 24
Finished	Jun 13 12:42:11 PM PDT 24
Peak memory	208844 kb
Host	smart-3f511d99-f2c7-41b2-bb87-b7bb83c610f4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258614865 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 48.kmac_test_vectors_kmac.2258614865 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2855652871
Short name	T236
Test name
Test status
Simulation time	247348285 ps
CPU time	4.54 seconds
Started	Jun 13 12:42:05 PM PDT 24
Finished	Jun 13 12:42:09 PM PDT 24
Peak memory	215816 kb
Host	smart-17e6c733-df35-4ddb-aa4c-78a196e3d10f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855652871 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2855652871 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_224.1579028784
Short name	T1012
Test name
Test status
Simulation time	486401751826 ps
CPU time	2135.54 seconds
Started	Jun 13 12:41:53 PM PDT 24
Finished	Jun 13 01:17:29 PM PDT 24
Peak memory	392460 kb
Host	smart-fb682e61-2a4a-4e26-a02d-45b68cc479ed
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1579028784 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.1579028784 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_256.889333469
Short name	T322
Test name
Test status
Simulation time	17402547123 ps
CPU time	1375.83 seconds
Started	Jun 13 12:41:52 PM PDT 24
Finished	Jun 13 01:04:49 PM PDT 24
Peak memory	366304 kb
Host	smart-b2499c40-1e10-4cb3-b5e3-c2a8f25fde1a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=889333469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.889333469 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_384.3571903845
Short name	T803
Test name
Test status
Simulation time	55938503328 ps
CPU time	1198.37 seconds
Started	Jun 13 12:41:59 PM PDT 24
Finished	Jun 13 01:01:58 PM PDT 24
Peak memory	330872 kb
Host	smart-05a202fd-b656-400b-853c-9c4caa268e7d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3571903845 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.3571903845 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_sha3_512.1860852097
Short name	T287
Test name
Test status
Simulation time	88205183516 ps
CPU time	872.9 seconds
Started	Jun 13 12:42:00 PM PDT 24
Finished	Jun 13 12:56:34 PM PDT 24
Peak memory	294512 kb
Host	smart-e82d1bba-ba8a-4a05-88c4-c7425555bcbf
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1860852097 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1860852097 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_128.3481360136
Short name	T570
Test name
Test status
Simulation time	719851551291 ps
CPU time	4830.36 seconds
Started	Jun 13 12:42:01 PM PDT 24
Finished	Jun 13 02:02:33 PM PDT 24
Peak memory	655656 kb
Host	smart-671dbfbe-1a86-42f4-8800-fe80b94a5373
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3481360136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.3481360136 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/48.kmac_test_vectors_shake_256.1228506089
Short name	T417
Test name
Test status
Simulation time	236767783241 ps
CPU time	4373.57 seconds
Started	Jun 13 12:42:07 PM PDT 24
Finished	Jun 13 01:55:01 PM PDT 24
Peak memory	566120 kb
Host	smart-cc80221a-58a6-449a-a0a3-9a8d13a60f21
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1228506089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1228506089 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/48.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/49.kmac_alert_test.3568221098
Short name	T658
Test name
Test status
Simulation time	25126356 ps
CPU time	0.77 seconds
Started	Jun 13 12:42:35 PM PDT 24
Finished	Jun 13 12:42:37 PM PDT 24
Peak memory	205244 kb
Host	smart-4862864e-a6a1-4c5d-9782-9bfeed146081
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568221098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.3568221098 +enable _masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_alert_test/latest

Test location	/workspace/coverage/default/49.kmac_app.988409470
Short name	T932
Test name
Test status
Simulation time	17071871803 ps
CPU time	249.77 seconds
Started	Jun 13 12:42:25 PM PDT 24
Finished	Jun 13 12:46:35 PM PDT 24
Peak memory	245736 kb
Host	smart-64c13fda-f8e6-426b-acfe-31750fa69aac
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988409470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.988409470 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_app/latest

Test location	/workspace/coverage/default/49.kmac_burst_write.2735390556
Short name	T121
Test name
Test status
Simulation time	36078832107 ps
CPU time	849.82 seconds
Started	Jun 13 12:42:16 PM PDT 24
Finished	Jun 13 12:56:27 PM PDT 24
Peak memory	231552 kb
Host	smart-07ee24ef-3c0d-4593-ab0c-a75d03d6a143
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2735390556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.2735390556 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_burst_write/latest

Test location	/workspace/coverage/default/49.kmac_entropy_refresh.663212161
Short name	T204
Test name
Test status
Simulation time	1270344446 ps
CPU time	21.57 seconds
Started	Jun 13 12:42:26 PM PDT 24
Finished	Jun 13 12:42:48 PM PDT 24
Peak memory	225020 kb
Host	smart-ebca069a-b8c8-4a24-8da5-d7eea42bf57e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=663212161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.663212161 +enable_masking=0 +sw _key_masked=0
Directory	/workspace/49.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/49.kmac_error.1967992888
Short name	T608
Test name
Test status
Simulation time	11818446928 ps
CPU time	210.24 seconds
Started	Jun 13 12:42:25 PM PDT 24
Finished	Jun 13 12:45:56 PM PDT 24
Peak memory	256684 kb
Host	smart-4fed4c4a-4c5c-4ab9-aa55-b881471c866d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1967992888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1967992888 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_error/latest

Test location	/workspace/coverage/default/49.kmac_key_error.3252562874
Short name	T62
Test name
Test status
Simulation time	1972112826 ps
CPU time	7.88 seconds
Started	Jun 13 12:42:28 PM PDT 24
Finished	Jun 13 12:42:37 PM PDT 24
Peak memory	215632 kb
Host	smart-be5af2d1-7f40-4284-bb21-bf6006a7b893
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3252562874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.3252562874 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_key_error/latest

Test location	/workspace/coverage/default/49.kmac_lc_escalation.1845531591
Short name	T283
Test name
Test status
Simulation time	37456175 ps
CPU time	1.31 seconds
Started	Jun 13 12:42:25 PM PDT 24
Finished	Jun 13 12:42:27 PM PDT 24
Peak memory	216856 kb
Host	smart-0f283fd2-5d90-45d1-99ea-2351514ed652
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845531591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.1845531591 +enable_masking=0 +sw_k ey_masked=0
Directory	/workspace/49.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/49.kmac_long_msg_and_output.648500035
Short name	T761
Test name
Test status
Simulation time	7479137792 ps
CPU time	320.42 seconds
Started	Jun 13 12:42:18 PM PDT 24
Finished	Jun 13 12:47:39 PM PDT 24
Peak memory	252948 kb
Host	smart-d3cbff4f-4890-4904-8fbb-7f463991204e
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648500035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_an d_output.648500035 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/49.kmac_sideload.3854111228
Short name	T1068
Test name
Test status
Simulation time	15654316142 ps
CPU time	105.75 seconds
Started	Jun 13 12:42:18 PM PDT 24
Finished	Jun 13 12:44:04 PM PDT 24
Peak memory	227364 kb
Host	smart-3ce33823-e429-4c3a-80f7-aa2d7931653f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854111228 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.3854111228 +e nable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_sideload/latest

Test location	/workspace/coverage/default/49.kmac_smoke.772201709
Short name	T640
Test name
Test status
Simulation time	212608326 ps
CPU time	2.91 seconds
Started	Jun 13 12:42:12 PM PDT 24
Finished	Jun 13 12:42:15 PM PDT 24
Peak memory	218752 kb
Host	smart-cb46314c-031e-436b-9d68-2b5bdce314d3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772201709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.772201709 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_smoke/latest

Test location	/workspace/coverage/default/49.kmac_stress_all.2889815752
Short name	T234
Test name
Test status
Simulation time	4787025636 ps
CPU time	61.17 seconds
Started	Jun 13 12:42:22 PM PDT 24
Finished	Jun 13 12:43:24 PM PDT 24
Peak memory	225208 kb
Host	smart-e6824793-6fab-4973-abf1-7251991f5b92
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2889815752 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2889815752 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_stress_all/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac.1075313399
Short name	T2
Test name
Test status
Simulation time	817189320 ps
CPU time	5.07 seconds
Started	Jun 13 12:42:26 PM PDT 24
Finished	Jun 13 12:42:32 PM PDT 24
Peak memory	215776 kb
Host	smart-2be73578-4bd3-4d5c-ac03-8bac8c781e39
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075313399 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 49.kmac_test_vectors_kmac.1075313399 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2028666714
Short name	T529
Test name
Test status
Simulation time	179054954 ps
CPU time	4.71 seconds
Started	Jun 13 12:42:25 PM PDT 24
Finished	Jun 13 12:42:30 PM PDT 24
Peak memory	215852 kb
Host	smart-1ea49b50-f372-416e-8a55-710341ac718f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028666714 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2028666714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_224.2655207229
Short name	T647
Test name
Test status
Simulation time	19242406241 ps
CPU time	1556.5 seconds
Started	Jun 13 12:42:17 PM PDT 24
Finished	Jun 13 01:08:15 PM PDT 24
Peak memory	377204 kb
Host	smart-1f9b6131-0323-40f6-a7b3-73a5263f4b6a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2655207229 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.2655207229 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_256.3791096381
Short name	T1059
Test name
Test status
Simulation time	310796708703 ps
CPU time	1697.2 seconds
Started	Jun 13 12:42:18 PM PDT 24
Finished	Jun 13 01:10:36 PM PDT 24
Peak memory	387512 kb
Host	smart-bad2476f-4e3d-43e5-8d62-2dd09952cbdc
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3791096381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.3791096381 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_384.2278903682
Short name	T218
Test name
Test status
Simulation time	173632246403 ps
CPU time	1141.72 seconds
Started	Jun 13 12:42:24 PM PDT 24
Finished	Jun 13 01:01:26 PM PDT 24
Peak memory	340572 kb
Host	smart-3670d6e6-f675-4b69-ac14-1646f47be669
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2278903682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.2278903682 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_sha3_512.2413802853
Short name	T223
Test name
Test status
Simulation time	33713556322 ps
CPU time	943.67 seconds
Started	Jun 13 12:42:26 PM PDT 24
Finished	Jun 13 12:58:10 PM PDT 24
Peak memory	295720 kb
Host	smart-9b6366ea-d2e5-49aa-b396-ef4a0acc4ff6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2413802853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.2413802853 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_128.2801332631
Short name	T797
Test name
Test status
Simulation time	173241684704 ps
CPU time	4651.64 seconds
Started	Jun 13 12:42:24 PM PDT 24
Finished	Jun 13 01:59:57 PM PDT 24
Peak memory	656968 kb
Host	smart-214dcd13-e4e3-4a95-b055-545d6b8e6627
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2801332631 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2801332631 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/49.kmac_test_vectors_shake_256.775345945
Short name	T303
Test name
Test status
Simulation time	604326827006 ps
CPU time	3963.23 seconds
Started	Jun 13 12:42:26 PM PDT 24
Finished	Jun 13 01:48:30 PM PDT 24
Peak memory	559396 kb
Host	smart-b4f0e772-845e-411a-9f3e-0a45649814f8
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=775345945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.775345945 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/49.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/5.kmac_alert_test.1184361516
Short name	T169
Test name
Test status
Simulation time	128537487 ps
CPU time	0.77 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:19 PM PDT 24
Peak memory	205236 kb
Host	smart-5c41f084-603c-4775-8f66-889a66a61f99
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184361516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.1184361516 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_alert_test/latest

Test location	/workspace/coverage/default/5.kmac_app.4094928840
Short name	T950
Test name
Test status
Simulation time	19841324532 ps
CPU time	238.28 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:41:17 PM PDT 24
Peak memory	239724 kb
Host	smart-4ae7871e-8a77-4100-a1d5-17b39dc28958
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094928840 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.4094928840 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_app/latest

Test location	/workspace/coverage/default/5.kmac_app_with_partial_data.621078944
Short name	T462
Test name
Test status
Simulation time	17347036038 ps
CPU time	287.61 seconds
Started	Jun 13 12:36:57 PM PDT 24
Finished	Jun 13 12:41:45 PM PDT 24
Peak memory	243036 kb
Host	smart-b34698ce-7077-483c-9b25-657fc81d2e71
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=621078944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.621078944 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/5.kmac_burst_write.838360128
Short name	T662
Test name
Test status
Simulation time	21441156899 ps
CPU time	172.75 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:40:06 PM PDT 24
Peak memory	224076 kb
Host	smart-33d28168-28ee-4faf-90aa-8d086bb57181
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=838360128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.838360128 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_burst_write/latest

Test location	/workspace/coverage/default/5.kmac_edn_timeout_error.2914825954
Short name	T168
Test name
Test status
Simulation time	42242347 ps
CPU time	2.74 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:37:37 PM PDT 24
Peak memory	215560 kb
Host	smart-6bf65117-ea4e-4f16-b781-ef3bd31c81ba
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2914825954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.2914825954 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_mode_error.4016941946
Short name	T528
Test name
Test status
Simulation time	388744180 ps
CPU time	29.64 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:37:40 PM PDT 24
Peak memory	220504 kb
Host	smart-84002679-c12d-4de6-9a24-4b95c4b445a4
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=4016941946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.4016941946 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_ready_error.3361766232
Short name	T47
Test name
Test status
Simulation time	58326690379 ps
CPU time	53.23 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:38:13 PM PDT 24
Peak memory	216976 kb
Host	smart-1c908254-992e-441f-8a16-74596720d68e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3361766232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3361766232 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/5.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/5.kmac_entropy_refresh.4058038419
Short name	T28
Test name
Test status
Simulation time	6509552326 ps
CPU time	32.05 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 12:38:03 PM PDT 24
Peak memory	224016 kb
Host	smart-6ef3a475-161a-4171-a702-5ec6493adc33
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4058038419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.4058038419 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/5.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/5.kmac_error.1708957975
Short name	T917
Test name
Test status
Simulation time	9303115409 ps
CPU time	88.73 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:38:45 PM PDT 24
Peak memory	236392 kb
Host	smart-7d261971-3980-4dc0-b8a1-67c2a7cd2bbf
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1708957975 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1708957975 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_error/latest

Test location	/workspace/coverage/default/5.kmac_key_error.2011775201
Short name	T664
Test name
Test status
Simulation time	6470876182 ps
CPU time	8.57 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 12:37:46 PM PDT 24
Peak memory	207456 kb
Host	smart-303ac470-af30-49af-9ed5-6f36ee3627f4
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2011775201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.2011775201 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_key_error/latest

Test location	/workspace/coverage/default/5.kmac_lc_escalation.4215287583
Short name	T53
Test name
Test status
Simulation time	44613925 ps
CPU time	1.44 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:37:11 PM PDT 24
Peak memory	220044 kb
Host	smart-992d9bdf-64e3-45c6-8bf7-b937e215fb3f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4215287583 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.4215287583 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/5.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/5.kmac_long_msg_and_output.3362096466
Short name	T1087
Test name
Test status
Simulation time	99677355606 ps
CPU time	1375.69 seconds
Started	Jun 13 12:37:06 PM PDT 24
Finished	Jun 13 01:00:04 PM PDT 24
Peak memory	370148 kb
Host	smart-d04da05a-f2e2-42f6-8c98-f71c17d9fa3a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362096466 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an d_output.3362096466 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/5.kmac_mubi.2040539836
Short name	T748
Test name
Test status
Simulation time	27203668632 ps
CPU time	268.86 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:41:49 PM PDT 24
Peak memory	243244 kb
Host	smart-267a4b0e-8946-4dbf-9a5b-c19c416ba78c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040539836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.2040539836 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_mubi/latest

Test location	/workspace/coverage/default/5.kmac_sideload.3589084427
Short name	T612
Test name
Test status
Simulation time	174541281826 ps
CPU time	228.46 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:41:11 PM PDT 24
Peak memory	241116 kb
Host	smart-7aab2134-7280-45e5-b857-d558886b28cd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589084427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.3589084427 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_sideload/latest

Test location	/workspace/coverage/default/5.kmac_smoke.47546356
Short name	T1078
Test name
Test status
Simulation time	2664718976 ps
CPU time	58.08 seconds
Started	Jun 13 12:36:58 PM PDT 24
Finished	Jun 13 12:37:57 PM PDT 24
Peak memory	219284 kb
Host	smart-807a1c27-759c-491d-b7c2-150f5c4a4120
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47546356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.47546356 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_smoke/latest

Test location	/workspace/coverage/default/5.kmac_stress_all.2986555677
Short name	T630
Test name
Test status
Simulation time	214322561984 ps
CPU time	1140.54 seconds
Started	Jun 13 12:36:53 PM PDT 24
Finished	Jun 13 12:55:57 PM PDT 24
Peak memory	364620 kb
Host	smart-7e678e1e-120e-4753-86f3-b19285ebb40b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2986555677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.2986555677 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_stress_all/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac.4102197740
Short name	T826
Test name
Test status
Simulation time	487156656 ps
CPU time	4.93 seconds
Started	Jun 13 12:36:59 PM PDT 24
Finished	Jun 13 12:37:05 PM PDT 24
Peak memory	208756 kb
Host	smart-3af8a0b3-dd4a-4ab7-9476-501f3bf7e1b2
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102197740 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 5.kmac_test_vectors_kmac.4102197740 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_kmac_xof.259786420
Short name	T261
Test name
Test status
Simulation time	232819982 ps
CPU time	3.71 seconds
Started	Jun 13 12:37:33 PM PDT 24
Finished	Jun 13 12:37:38 PM PDT 24
Peak memory	215824 kb
Host	smart-b1d08ef0-ed60-488e-903f-4cc879e57d6f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259786420 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 5.kmac_test_vectors_kmac_xof.259786420 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_224.2153595262
Short name	T179
Test name
Test status
Simulation time	403152638673 ps
CPU time	1712.83 seconds
Started	Jun 13 12:37:04 PM PDT 24
Finished	Jun 13 01:05:38 PM PDT 24
Peak memory	389800 kb
Host	smart-f3511fd4-0f74-488a-8f9d-c49b981e7be6
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2153595262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.2153595262 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_256.3231893740
Short name	T1035
Test name
Test status
Simulation time	42152178744 ps
CPU time	1471.6 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 01:01:44 PM PDT 24
Peak memory	373808 kb
Host	smart-ca1afc5a-6fda-4021-b324-c48e74e45de0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3231893740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.3231893740 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_384.2826298650
Short name	T233
Test name
Test status
Simulation time	61821883176 ps
CPU time	1081.58 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:55:14 PM PDT 24
Peak memory	334416 kb
Host	smart-a77ee804-577e-4f55-bea7-b4be128bfa1c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2826298650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2826298650 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_sha3_512.2678546827
Short name	T1030
Test name
Test status
Simulation time	66854504696 ps
CPU time	839.52 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:51:22 PM PDT 24
Peak memory	291492 kb
Host	smart-2f9523d8-9727-4af0-a660-9d1d2b794507
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2678546827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.2678546827 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_128.1368371526
Short name	T990
Test name
Test status
Simulation time	422917511271 ps
CPU time	4247.36 seconds
Started	Jun 13 12:37:34 PM PDT 24
Finished	Jun 13 01:48:23 PM PDT 24
Peak memory	648632 kb
Host	smart-ab69bf90-5211-425d-8099-52b43d0cc46a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1368371526 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.1368371526 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/5.kmac_test_vectors_shake_256.2516243969
Short name	T557
Test name
Test status
Simulation time	135274707330 ps
CPU time	3447.55 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 01:34:48 PM PDT 24
Peak memory	562280 kb
Host	smart-3b9f608d-c0b3-4d92-8150-af8a06922b73
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2516243969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.2516243969 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/5.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/6.kmac_alert_test.474065049
Short name	T654
Test name
Test status
Simulation time	70712587 ps
CPU time	0.82 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:37:20 PM PDT 24
Peak memory	205228 kb
Host	smart-368c003d-fc61-4cbf-99bb-94c565ee8749
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474065049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.474065049 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_alert_test/latest

Test location	/workspace/coverage/default/6.kmac_app.3846772472
Short name	T609
Test name
Test status
Simulation time	26074798305 ps
CPU time	141.03 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:39:32 PM PDT 24
Peak memory	234596 kb
Host	smart-47fecd07-2db9-4454-b6f6-100fe7e10e9b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3846772472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.3846772472 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_app/latest

Test location	/workspace/coverage/default/6.kmac_app_with_partial_data.2054721022
Short name	T935
Test name
Test status
Simulation time	2086023148 ps
CPU time	78.77 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:38:34 PM PDT 24
Peak memory	228324 kb
Host	smart-bf12e135-1571-4c19-abac-ec71ee86758f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2054721022 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.2054721022 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/6.kmac_burst_write.159556903
Short name	T229
Test name
Test status
Simulation time	3786340277 ps
CPU time	28.98 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:37:40 PM PDT 24
Peak memory	222840 kb
Host	smart-42407a80-8bd7-4a62-97dc-e77622cccb45
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=159556903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.159556903 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_burst_write/latest

Test location	/workspace/coverage/default/6.kmac_edn_timeout_error.2865157263
Short name	T1048
Test name
Test status
Simulation time	37346471 ps
CPU time	2.98 seconds
Started	Jun 13 12:37:26 PM PDT 24
Finished	Jun 13 12:37:31 PM PDT 24
Peak memory	215520 kb
Host	smart-03180b18-76ba-420b-abe0-770d7d57b878
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2865157263 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2865157263 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_mode_error.2310973181
Short name	T354
Test name
Test status
Simulation time	1270692521 ps
CPU time	32.76 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:38:10 PM PDT 24
Peak memory	220688 kb
Host	smart-ef3edfe1-d2f8-45aa-b947-afe9b13905e0
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2310973181 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.2310973181 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_ready_error.2646312507
Short name	T965
Test name
Test status
Simulation time	13577169548 ps
CPU time	60.65 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:38:14 PM PDT 24
Peak memory	216608 kb
Host	smart-ca3efc35-93f2-429a-a3be-f354fd5fe588
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2646312507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2646312507 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/6.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/6.kmac_entropy_refresh.405512770
Short name	T372
Test name
Test status
Simulation time	6062797124 ps
CPU time	32.76 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:37:50 PM PDT 24
Peak memory	224068 kb
Host	smart-a5ea5339-5d79-4a98-9baa-d24050c5c2b6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=405512770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.405512770 +enable_masking=0 +sw_ key_masked=0
Directory	/workspace/6.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/6.kmac_error.3199449683
Short name	T670
Test name
Test status
Simulation time	2676063343 ps
CPU time	59.51 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:38:18 PM PDT 24
Peak memory	233144 kb
Host	smart-5aef5ed3-c616-49bd-ae17-4ac39cb31d17
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3199449683 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3199449683 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_error/latest

Test location	/workspace/coverage/default/6.kmac_key_error.2112346302
Short name	T20
Test name
Test status
Simulation time	2539564146 ps
CPU time	7.73 seconds
Started	Jun 13 12:37:23 PM PDT 24
Finished	Jun 13 12:37:33 PM PDT 24
Peak memory	207472 kb
Host	smart-f160e680-6502-4853-b16b-1b75e04c645a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2112346302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2112346302 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_key_error/latest

Test location	/workspace/coverage/default/6.kmac_lc_escalation.3038377439
Short name	T1044
Test name
Test status
Simulation time	10330329234 ps
CPU time	11.12 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:37:21 PM PDT 24
Peak memory	221900 kb
Host	smart-0f1834cf-62fa-44cb-a925-ca93c55a6211
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3038377439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.3038377439 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/6.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/6.kmac_long_msg_and_output.2202222102
Short name	T1016
Test name
Test status
Simulation time	27502950259 ps
CPU time	792.43 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:50:29 PM PDT 24
Peak memory	292388 kb
Host	smart-43ee9793-9f50-4d7e-b47d-796ee5bd6725
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202222102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an d_output.2202222102 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/6.kmac_mubi.3085463366
Short name	T432
Test name
Test status
Simulation time	35030088611 ps
CPU time	74.42 seconds
Started	Jun 13 12:37:25 PM PDT 24
Finished	Jun 13 12:38:40 PM PDT 24
Peak memory	226376 kb
Host	smart-f61f2ea8-3c8a-47c6-acdc-35942c2b09a0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3085463366 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.3085463366 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_mubi/latest

Test location	/workspace/coverage/default/6.kmac_sideload.1191878993
Short name	T515
Test name
Test status
Simulation time	7487298498 ps
CPU time	156.58 seconds
Started	Jun 13 12:37:05 PM PDT 24
Finished	Jun 13 12:39:44 PM PDT 24
Peak memory	233540 kb
Host	smart-2a35b711-e5bf-4450-9fea-456e42e21b11
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191878993 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.1191878993 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_sideload/latest

Test location	/workspace/coverage/default/6.kmac_smoke.387040608
Short name	T947
Test name
Test status
Simulation time	1743268584 ps
CPU time	33.48 seconds
Started	Jun 13 12:36:51 PM PDT 24
Finished	Jun 13 12:37:28 PM PDT 24
Peak memory	219200 kb
Host	smart-e72445e7-efb7-427e-9ec8-3301eed85d52
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=387040608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.387040608 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_smoke/latest

Test location	/workspace/coverage/default/6.kmac_stress_all.3777929365
Short name	T847
Test name
Test status
Simulation time	111098085357 ps
CPU time	660.78 seconds
Started	Jun 13 12:37:44 PM PDT 24
Finished	Jun 13 12:48:48 PM PDT 24
Peak memory	332496 kb
Host	smart-73effffa-6a35-4c87-9e68-a46a1e744c7a
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3777929365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.3777929365 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_stress_all/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac.584097407
Short name	T254
Test name
Test status
Simulation time	3455754246 ps
CPU time	5.94 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:37:30 PM PDT 24
Peak memory	215852 kb
Host	smart-5297c3b6-6fa0-4b99-aab4-bad23990ce06
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584097407 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 6.kmac_test_vectors_kmac.584097407 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_kmac_xof.3442855791
Short name	T867
Test name
Test status
Simulation time	1457958118 ps
CPU time	5.16 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:37:29 PM PDT 24
Peak memory	215776 kb
Host	smart-fc757799-a9ed-489a-a246-b36942974a12
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442855791 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_kmac_xof.3442855791 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_224.651524162
Short name	T649
Test name
Test status
Simulation time	807894292898 ps
CPU time	2083.18 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 01:11:55 PM PDT 24
Peak memory	390824 kb
Host	smart-4d3195a5-1e96-45d0-af90-9d387c559b3a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=651524162 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.651524162 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_256.3368305914
Short name	T895
Test name
Test status
Simulation time	72916341697 ps
CPU time	1441.68 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 01:02:31 PM PDT 24
Peak memory	390408 kb
Host	smart-388400b4-c21f-4159-b600-ed3db02bac6a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3368305914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.3368305914 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_384.1336618428
Short name	T535
Test name
Test status
Simulation time	62187365592 ps
CPU time	1072.01 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:55:06 PM PDT 24
Peak memory	335688 kb
Host	smart-950839f6-b1b3-42bc-a7f6-01b3c4ef0669
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1336618428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.1336618428 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_sha3_512.820661140
Short name	T1088
Test name
Test status
Simulation time	129020611079 ps
CPU time	795.46 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:51:29 PM PDT 24
Peak memory	292612 kb
Host	smart-da993be6-8331-4171-8f1f-0ce8bd94d083
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=820661140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.820661140 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_128.76263165
Short name	T197
Test name
Test status
Simulation time	174732484086 ps
CPU time	4511.63 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 01:52:34 PM PDT 24
Peak memory	646096 kb
Host	smart-247cbb38-848e-488a-b112-62b209147c77
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=76263165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.76263165 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/6.kmac_test_vectors_shake_256.3544709893
Short name	T795
Test name
Test status
Simulation time	169595176680 ps
CPU time	3379.05 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 01:33:39 PM PDT 24
Peak memory	541640 kb
Host	smart-cd96ce24-8a4c-4592-8c33-765820e0a97f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3544709893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.3544709893 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/6.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/7.kmac_alert_test.1270315570
Short name	T294
Test name
Test status
Simulation time	17894957 ps
CPU time	0.81 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	205192 kb
Host	smart-7976888c-785f-444c-a608-7134336ae055
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270315570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.1270315570 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_alert_test/latest

Test location	/workspace/coverage/default/7.kmac_app.517669487
Short name	T887
Test name
Test status
Simulation time	9192122857 ps
CPU time	183.06 seconds
Started	Jun 13 12:37:53 PM PDT 24
Finished	Jun 13 12:40:57 PM PDT 24
Peak memory	240064 kb
Host	smart-a2f54ada-9ac4-4ac9-822b-98a1ce9e9a1a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517669487 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.517669487 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_app/latest

Test location	/workspace/coverage/default/7.kmac_app_with_partial_data.2079275221
Short name	T323
Test name
Test status
Simulation time	17712889921 ps
CPU time	140.75 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:39:30 PM PDT 24
Peak memory	232088 kb
Host	smart-1ecb76f3-f0fa-47e3-863a-23aca9b0722a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2079275221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.2079275221 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/7.kmac_burst_write.4212193342
Short name	T905
Test name
Test status
Simulation time	4334477354 ps
CPU time	191.39 seconds
Started	Jun 13 12:37:07 PM PDT 24
Finished	Jun 13 12:40:20 PM PDT 24
Peak memory	224192 kb
Host	smart-0cf3e347-d9f5-43c6-bbeb-ca7fb10fc4d1
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212193342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.4212193342 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_burst_write/latest

Test location	/workspace/coverage/default/7.kmac_edn_timeout_error.412414747
Short name	T707
Test name
Test status
Simulation time	453022485 ps
CPU time	34.09 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:37:48 PM PDT 24
Peak memory	229196 kb
Host	smart-7128561c-13b6-4eed-9d63-19241b89e209
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=412414747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.412414747 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_mode_error.1196871057
Short name	T185
Test name
Test status
Simulation time	320117520 ps
CPU time	6.57 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:19 PM PDT 24
Peak memory	218296 kb
Host	smart-3868719e-dbda-4017-bf7e-3b5d68ccb2c9
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1196871057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.1196871057 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_ready_error.1788475852
Short name	T48
Test name
Test status
Simulation time	17780578973 ps
CPU time	48.33 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 12:38:05 PM PDT 24
Peak memory	224004 kb
Host	smart-387f3029-156d-467a-ae90-61f502957eb7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1788475852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1788475852 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/7.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/7.kmac_entropy_refresh.803013615
Short name	T222
Test name
Test status
Simulation time	38290853926 ps
CPU time	147.23 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:40:56 PM PDT 24
Peak memory	235416 kb
Host	smart-adfacd00-1715-460e-bbee-7042a27f15b3
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=803013615 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.803013615 +enable_masking=0 +sw_ key_masked=0
Directory	/workspace/7.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/7.kmac_error.4040745164
Short name	T818
Test name
Test status
Simulation time	69253911696 ps
CPU time	341.76 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:42:59 PM PDT 24
Peak memory	256784 kb
Host	smart-f6060d53-ce31-4846-9d8c-dbca9a5b3f81
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4040745164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.4040745164 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_error/latest

Test location	/workspace/coverage/default/7.kmac_key_error.1766493877
Short name	T403
Test name
Test status
Simulation time	6391593915 ps
CPU time	7.24 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:37:26 PM PDT 24
Peak memory	215688 kb
Host	smart-44e40281-bd4e-4df4-8d64-70f170d81ae7
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1766493877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.1766493877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_key_error/latest

Test location	/workspace/coverage/default/7.kmac_lc_escalation.1717377418
Short name	T79
Test name
Test status
Simulation time	97669415 ps
CPU time	1.37 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:37:22 PM PDT 24
Peak memory	215720 kb
Host	smart-11b2ec5c-4c30-4ca5-a3e1-3fac10bd36c5
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1717377418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1717377418 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/7.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/7.kmac_long_msg_and_output.3396170450
Short name	T614
Test name
Test status
Simulation time	54592470311 ps
CPU time	388.22 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:44:57 PM PDT 24
Peak memory	255444 kb
Host	smart-50c1db21-3f6c-4fc8-a211-59317e73551b
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396170450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an d_output.3396170450 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/7.kmac_mubi.650291467
Short name	T650
Test name
Test status
Simulation time	36580903355 ps
CPU time	326.04 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:42:49 PM PDT 24
Peak memory	247500 kb
Host	smart-dc546eae-07f3-4dfa-98d0-b967b016666b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=650291467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.650291467 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_mubi/latest

Test location	/workspace/coverage/default/7.kmac_sideload.3998798525
Short name	T823
Test name
Test status
Simulation time	26849077746 ps
CPU time	151.19 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:39:53 PM PDT 24
Peak memory	231384 kb
Host	smart-c12d9383-37c2-4417-b22e-3b2a28cddebd
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998798525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.3998798525 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_sideload/latest

Test location	/workspace/coverage/default/7.kmac_smoke.1035300604
Short name	T165
Test name
Test status
Simulation time	4931427067 ps
CPU time	28.75 seconds
Started	Jun 13 12:37:08 PM PDT 24
Finished	Jun 13 12:37:39 PM PDT 24
Peak memory	218776 kb
Host	smart-ba34892e-2773-4104-979c-cfa773f4dd79
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1035300604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.1035300604 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_smoke/latest

Test location	/workspace/coverage/default/7.kmac_stress_all.1620878836
Short name	T474
Test name
Test status
Simulation time	65948840481 ps
CPU time	1263.96 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:58:21 PM PDT 24
Peak memory	376376 kb
Host	smart-5bdda9c6-4d2c-440b-9aa4-8629a7c1d262
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1620878836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1620878836 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_stress_all/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac.3462476833
Short name	T1060
Test name
Test status
Simulation time	166975884 ps
CPU time	4.17 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 12:37:19 PM PDT 24
Peak memory	215776 kb
Host	smart-01ac65b5-e9ba-4891-ba69-bef0b85a0492
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462476833 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 7.kmac_test_vectors_kmac.3462476833 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1496812307
Short name	T543
Test name
Test status
Simulation time	879550800 ps
CPU time	4.54 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:37:18 PM PDT 24
Peak memory	215796 kb
Host	smart-8238f4f8-010d-490a-b36e-7a0455cfca2c
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496812307 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1496812307 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_224.672833763
Short name	T524
Test name
Test status
Simulation time	262073646820 ps
CPU time	1758.42 seconds
Started	Jun 13 12:38:11 PM PDT 24
Finished	Jun 13 01:07:30 PM PDT 24
Peak memory	395676 kb
Host	smart-8019830d-f314-4b02-ab4a-55a943ac3a5f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=672833763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.672833763 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_256.1713151900
Short name	T378
Test name
Test status
Simulation time	98711253530 ps
CPU time	1451.38 seconds
Started	Jun 13 12:37:14 PM PDT 24
Finished	Jun 13 01:01:29 PM PDT 24
Peak memory	375004 kb
Host	smart-70a0542a-baf5-4dec-badb-7b1418d93478
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1713151900 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.1713151900 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_384.783389714
Short name	T503
Test name
Test status
Simulation time	47134898563 ps
CPU time	1306.62 seconds
Started	Jun 13 12:37:09 PM PDT 24
Finished	Jun 13 12:58:57 PM PDT 24
Peak memory	336576 kb
Host	smart-b7638abd-b9fb-4eff-bb2b-94cb883dfd69
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=783389714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.783389714 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_sha3_512.549139308
Short name	T302
Test name
Test status
Simulation time	10121287332 ps
CPU time	806.15 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:50:45 PM PDT 24
Peak memory	299384 kb
Host	smart-3ecf58eb-3cb6-400e-8a1e-7f8a1ae1c17d
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=549139308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.549139308 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_128.2156253135
Short name	T611
Test name
Test status
Simulation time	212923549471 ps
CPU time	3888.07 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 01:43:17 PM PDT 24
Peak memory	656104 kb
Host	smart-1dbd7550-d478-4991-9be8-25bc5b741dc4
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2156253135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.2156253135 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/7.kmac_test_vectors_shake_256.376622943
Short name	T187
Test name
Test status
Simulation time	1330269549072 ps
CPU time	3955.99 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 01:44:10 PM PDT 24
Peak memory	565848 kb
Host	smart-6e1b293c-aa79-4372-abeb-986f09abd3a5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=376622943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.376622943 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/7.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/8.kmac_alert_test.2195595052
Short name	T50
Test name
Test status
Simulation time	46700328 ps
CPU time	0.76 seconds
Started	Jun 13 12:37:29 PM PDT 24
Finished	Jun 13 12:37:31 PM PDT 24
Peak memory	205148 kb
Host	smart-b3ab4982-2d10-4c1d-85b4-32d73a4ed86c
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195595052 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.2195595052 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_alert_test/latest

Test location	/workspace/coverage/default/8.kmac_app.2754202138
Short name	T677
Test name
Test status
Simulation time	18718775244 ps
CPU time	41.67 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:39:11 PM PDT 24
Peak memory	222896 kb
Host	smart-ec047989-d9fa-40c9-bea4-58f799fffb89
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2754202138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.2754202138 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_app/latest

Test location	/workspace/coverage/default/8.kmac_app_with_partial_data.3585396277
Short name	T136
Test name
Test status
Simulation time	20209843596 ps
CPU time	211.86 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:40:54 PM PDT 24
Peak memory	244980 kb
Host	smart-3e2f1c4e-378a-43b7-824f-67b928183ea8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3585396277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3585396277 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/8.kmac_burst_write.3056086071
Short name	T122
Test name
Test status
Simulation time	52267390652 ps
CPU time	136.08 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:39:37 PM PDT 24
Peak memory	224248 kb
Host	smart-311293f8-29fe-4372-966d-46e80696e933
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056086071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.3056086071 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_burst_write/latest

Test location	/workspace/coverage/default/8.kmac_edn_timeout_error.2477420074
Short name	T580
Test name
Test status
Simulation time	2073397151 ps
CPU time	12.83 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:38:41 PM PDT 24
Peak memory	216440 kb
Host	smart-623007d0-aaba-40ec-a40e-b7cfca35b9c1
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=2477420074 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2477420074 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_mode_error.1167629725
Short name	T620
Test name
Test status
Simulation time	725812188 ps
CPU time	5.46 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	215588 kb
Host	smart-5d7c292d-b6cd-45dc-9240-2dee9176a916
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1167629725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.1167629725 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/8.kmac_entropy_ready_error.220329822
Short name	T1013
Test name
Test status
Simulation time	674596759 ps
CPU time	5.43 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:38:33 PM PDT 24
Peak memory	215624 kb
Host	smart-2acfe443-bde4-4af5-a2c9-303cf8185be6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=220329822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.220329822 +enable_maskin g=0 +sw_key_masked=0
Directory	/workspace/8.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/8.kmac_error.1827874728
Short name	T774
Test name
Test status
Simulation time	4113526068 ps
CPU time	107.77 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:39:00 PM PDT 24
Peak memory	238980 kb
Host	smart-e2d33822-98e8-448e-b2cf-19c2c9f95d8a
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1827874728 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1827874728 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_error/latest

Test location	/workspace/coverage/default/8.kmac_key_error.2685217195
Short name	T859
Test name
Test status
Simulation time	1389216144 ps
CPU time	6.94 seconds
Started	Jun 13 12:38:27 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	207284 kb
Host	smart-495134d3-d279-4266-9f82-172471a6bbe6
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2685217195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.2685217195 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_key_error/latest

Test location	/workspace/coverage/default/8.kmac_lc_escalation.4143152459
Short name	T36
Test name
Test status
Simulation time	35978207 ps
CPU time	1.3 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	215860 kb
Host	smart-404fb397-e8e8-4377-8e18-be643f190ec0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4143152459 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.4143152459 +enable_masking=0 +sw_ke y_masked=0
Directory	/workspace/8.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/8.kmac_long_msg_and_output.682944701
Short name	T343
Test name
Test status
Simulation time	61599764265 ps
CPU time	757.78 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:50:50 PM PDT 24
Peak memory	303792 kb
Host	smart-ccfad4fe-6a25-4755-b289-2102e1ac85a1
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682944701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and _output.682944701 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/8.kmac_mubi.450747868
Short name	T696
Test name
Test status
Simulation time	20327795755 ps
CPU time	193.06 seconds
Started	Jun 13 12:37:10 PM PDT 24
Finished	Jun 13 12:40:25 PM PDT 24
Peak memory	237768 kb
Host	smart-77fa4aad-3b08-413a-b3b0-7d789b45ea36
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=450747868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.450747868 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_mubi/latest

Test location	/workspace/coverage/default/8.kmac_sideload.186707004
Short name	T861
Test name
Test status
Simulation time	35566748562 ps
CPU time	317.52 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:43:31 PM PDT 24
Peak memory	245148 kb
Host	smart-8a96ae74-63d8-4717-8d39-d05125c07b1f
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186707004 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.186707004 +enab le_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_sideload/latest

Test location	/workspace/coverage/default/8.kmac_smoke.2946121037
Short name	T928
Test name
Test status
Simulation time	60922405386 ps
CPU time	59.63 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 12:38:17 PM PDT 24
Peak memory	215872 kb
Host	smart-d5855bfd-accf-48cd-b640-55c4c7a5cf35
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2946121037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2946121037 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_smoke/latest

Test location	/workspace/coverage/default/8.kmac_stress_all.1018185180
Short name	T500
Test name
Test status
Simulation time	112226075940 ps
CPU time	666.95 seconds
Started	Jun 13 12:37:20 PM PDT 24
Finished	Jun 13 12:48:30 PM PDT 24
Peak memory	306388 kb
Host	smart-b430f5f3-5adb-4a26-9da5-76cc168eba49
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1018185180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.1018185180 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_stress_all/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac.470396097
Short name	T538
Test name
Test status
Simulation time	679653981 ps
CPU time	4.58 seconds
Started	Jun 13 12:38:12 PM PDT 24
Finished	Jun 13 12:38:17 PM PDT 24
Peak memory	215344 kb
Host	smart-d330a387-1f8a-4ee3-8c88-974e5c0fd5a9
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470396097 -assert nopostproc +UVM_TESTNAME=kmac_base_ test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 8.kmac_test_vectors_kmac.470396097 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_kmac_xof.3971916954
Short name	T741
Test name
Test status
Simulation time	262115550 ps
CPU time	4.01 seconds
Started	Jun 13 12:38:10 PM PDT 24
Finished	Jun 13 12:38:15 PM PDT 24
Peak memory	214364 kb
Host	smart-3545d181-ae85-4e71-8b3d-d4d2d141b22a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971916954 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_kmac_xof.3971916954 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_224.180957057
Short name	T4
Test name
Test status
Simulation time	22319966246 ps
CPU time	1545.85 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 01:03:06 PM PDT 24
Peak memory	399132 kb
Host	smart-7f73714e-d5f4-46fc-8451-55abf65912b0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=180957057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.180957057 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_256.1095530928
Short name	T678
Test name
Test status
Simulation time	60490501772 ps
CPU time	1587.75 seconds
Started	Jun 13 12:37:15 PM PDT 24
Finished	Jun 13 01:03:46 PM PDT 24
Peak memory	370648 kb
Host	smart-4ff7a76e-f91e-4163-83e4-5cfa09188702
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1095530928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.1095530928 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_384.3824492495
Short name	T681
Test name
Test status
Simulation time	13624540066 ps
CPU time	1155.03 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:56:28 PM PDT 24
Peak memory	334732 kb
Host	smart-04f5108c-c823-437f-aa35-cfa4a7346646
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3824492495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.3824492495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_sha3_512.124677495
Short name	T625
Test name
Test status
Simulation time	10036470900 ps
CPU time	788.49 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:50:29 PM PDT 24
Peak memory	297920 kb
Host	smart-58a10bb3-8ab7-43c4-a7b9-e6c0dab2d5e0
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=124677495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.124677495 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_128.773553803
Short name	T1058
Test name
Test status
Simulation time	52898149314 ps
CPU time	4185.88 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 01:47:19 PM PDT 24
Peak memory	648724 kb
Host	smart-c94311e9-74b1-427d-945a-5de0d49f375a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=773553803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.773553803 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/8.kmac_test_vectors_shake_256.281742273
Short name	T1022
Test name
Test status
Simulation time	182419743011 ps
CPU time	3300.47 seconds
Started	Jun 13 12:38:28 PM PDT 24
Finished	Jun 13 01:33:30 PM PDT 24
Peak memory	571188 kb
Host	smart-39c0d43a-41e0-4180-98e7-e74b5483fa93
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=281742273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.281742273 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/8.kmac_test_vectors_shake_256/latest

Test location	/workspace/coverage/default/9.kmac_alert_test.282760669
Short name	T666
Test name
Test status
Simulation time	72417023 ps
CPU time	0.85 seconds
Started	Jun 13 12:37:23 PM PDT 24
Finished	Jun 13 12:37:26 PM PDT 24
Peak memory	205196 kb
Host	smart-9fab67ed-fe4b-4c3b-a5ae-3f13d34d2cd5
User	root
Command	/workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282760669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.282760669 +enable_ma sking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_alert_test/latest

Test location	/workspace/coverage/default/9.kmac_app.3206358545
Short name	T471
Test name
Test status
Simulation time	3894150067 ps
CPU time	99 seconds
Started	Jun 13 12:37:36 PM PDT 24
Finished	Jun 13 12:39:16 PM PDT 24
Peak memory	232976 kb
Host	smart-da1b666b-7d29-454d-b41b-b6c21f9637a8
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3206358545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.3206358545 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_app/latest

Test location	/workspace/coverage/default/9.kmac_app_with_partial_data.2429886501
Short name	T90
Test name
Test status
Simulation time	9808806426 ps
CPU time	192.72 seconds
Started	Jun 13 12:37:24 PM PDT 24
Finished	Jun 13 12:40:38 PM PDT 24
Peak memory	238976 kb
Host	smart-e7acb63e-1e9b-4ea5-8808-4593f4b6054f
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2429886501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.2429886501 +enable_ masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_app_with_partial_data/latest

Test location	/workspace/coverage/default/9.kmac_burst_write.1500907339
Short name	T1049
Test name
Test status
Simulation time	7789647004 ps
CPU time	641.1 seconds
Started	Jun 13 12:37:13 PM PDT 24
Finished	Jun 13 12:47:57 PM PDT 24
Peak memory	232228 kb
Host	smart-b76aaac1-e062-4e32-a6db-226e59e36a1e
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500907339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1500907339 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_burst_write/latest

Test location	/workspace/coverage/default/9.kmac_edn_timeout_error.3907151744
Short name	T342
Test name
Test status
Simulation time	11930401794 ps
CPU time	24.33 seconds
Started	Jun 13 12:37:29 PM PDT 24
Finished	Jun 13 12:37:54 PM PDT 24
Peak memory	223760 kb
Host	smart-80936123-b2e0-4d43-a6ab-9744ccc3bb1c
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=3907151744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.3907151744 +enabl e_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_edn_timeout_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_mode_error.1043123298
Short name	T789
Test name
Test status
Simulation time	627505358 ps
CPU time	23.4 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:37:37 PM PDT 24
Peak memory	231948 kb
Host	smart-86d71fdf-97a3-4d41-ba9f-bf2c9846ba43
User	root
Command	/workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h w/dv/tools/sim.tcl +ntb_random_seed=1043123298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.1043123298 +ena ble_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_mode_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_ready_error.3882777907
Short name	T1021
Test name
Test status
Simulation time	42591611954 ps
CPU time	69.98 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:38:32 PM PDT 24
Peak memory	216748 kb
Host	smart-e9da682a-a83b-45df-8018-4f9a8aef2bbb
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3882777907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.3882777907 +enable_mask ing=0 +sw_key_masked=0
Directory	/workspace/9.kmac_entropy_ready_error/latest

Test location	/workspace/coverage/default/9.kmac_entropy_refresh.2248901443
Short name	T178
Test name
Test status
Simulation time	14878096934 ps
CPU time	61.95 seconds
Started	Jun 13 12:37:32 PM PDT 24
Finished	Jun 13 12:38:35 PM PDT 24
Peak memory	226848 kb
Host	smart-7fe1fe19-3f4f-467f-a52c-fcca901e215d
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2248901443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.2248901443 +enable_masking=0 +s w_key_masked=0
Directory	/workspace/9.kmac_entropy_refresh/latest

Test location	/workspace/coverage/default/9.kmac_error.2622383205
Short name	T711
Test name
Test status
Simulation time	875101306 ps
CPU time	22.7 seconds
Started	Jun 13 12:37:41 PM PDT 24
Finished	Jun 13 12:38:05 PM PDT 24
Peak memory	232060 kb
Host	smart-8e993618-eca7-40b5-91c5-47c9fbd4f741
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2622383205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2622383205 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_error/latest

Test location	/workspace/coverage/default/9.kmac_key_error.1694282476
Short name	T379
Test name
Test status
Simulation time	8468549190 ps
CPU time	5.39 seconds
Started	Jun 13 12:37:28 PM PDT 24
Finished	Jun 13 12:37:35 PM PDT 24
Peak memory	215680 kb
Host	smart-15f070a8-c7cc-4fe9-9faa-a9f2efc6f397
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1694282476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1694282476 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_key_error/latest

Test location	/workspace/coverage/default/9.kmac_lc_escalation.326040735
Short name	T722
Test name
Test status
Simulation time	48382151 ps
CPU time	1.31 seconds
Started	Jun 13 12:37:18 PM PDT 24
Finished	Jun 13 12:37:23 PM PDT 24
Peak memory	215780 kb
Host	smart-e0a6c517-9f80-4133-8e6f-91eeed0e8990
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326040735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.326040735 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_lc_escalation/latest

Test location	/workspace/coverage/default/9.kmac_long_msg_and_output.2260195444
Short name	T602
Test name
Test status
Simulation time	244405733296 ps
CPU time	1950.9 seconds
Started	Jun 13 12:37:29 PM PDT 24
Finished	Jun 13 01:10:01 PM PDT 24
Peak memory	452688 kb
Host	smart-050b7c3e-e372-4a3b-be2e-09ce009d9cb7
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260195444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_an d_output.2260195444 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_long_msg_and_output/latest

Test location	/workspace/coverage/default/9.kmac_mubi.2496241327
Short name	T314
Test name
Test status
Simulation time	10011975663 ps
CPU time	237.39 seconds
Started	Jun 13 12:37:23 PM PDT 24
Finished	Jun 13 12:41:22 PM PDT 24
Peak memory	242864 kb
Host	smart-f8d48361-b280-4ea2-aa6a-9f3ce6d4e90b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2496241327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.2496241327 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_mubi/latest

Test location	/workspace/coverage/default/9.kmac_sideload.1687130339
Short name	T672
Test name
Test status
Simulation time	19327167635 ps
CPU time	201.28 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 12:40:40 PM PDT 24
Peak memory	238640 kb
Host	smart-c2ac1a76-8db9-44d7-a8cd-ea1ebdeeb4d4
User	root
Command	/workspace/default/simv +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687130339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.1687130339 +en able_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_sideload/latest

Test location	/workspace/coverage/default/9.kmac_smoke.422505877
Short name	T445
Test name
Test status
Simulation time	2220217651 ps
CPU time	36.87 seconds
Started	Jun 13 12:37:21 PM PDT 24
Finished	Jun 13 12:38:00 PM PDT 24
Peak memory	218548 kb
Host	smart-6f651177-cb4b-466a-b92c-1b85abf5f1ee
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422505877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.422505877 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_smoke/latest

Test location	/workspace/coverage/default/9.kmac_stress_all.777587876
Short name	T925
Test name
Test status
Simulation time	292649282052 ps
CPU time	1351.43 seconds
Started	Jun 13 12:37:17 PM PDT 24
Finished	Jun 13 12:59:52 PM PDT 24
Peak memory	378824 kb
Host	smart-bb4e739a-20bd-43a2-84f7-fda2e84eb901
User	root
Command	/workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=777587876 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.777587876 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_stress_all/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac.2114537552
Short name	T955
Test name
Test status
Simulation time	234126519 ps
CPU time	3.84 seconds
Started	Jun 13 12:37:19 PM PDT 24
Finished	Jun 13 12:37:26 PM PDT 24
Peak memory	215784 kb
Host	smart-ce4c54d6-b4d6-43ef-a3b5-a81542782499
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114537552 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 9.kmac_test_vectors_kmac.2114537552 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_kmac_xof.2062186473
Short name	T1070
Test name
Test status
Simulation time	672085645 ps
CPU time	4.8 seconds
Started	Jun 13 12:37:40 PM PDT 24
Finished	Jun 13 12:37:46 PM PDT 24
Peak memory	215828 kb
Host	smart-92c19887-57cd-4bf7-8837-5f92d55f831a
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062186473 -assert nopostproc +UVM_TESTNAME=kmac_base _test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_kmac_xof.2062186473 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_kmac_xof/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_224.1082747106
Short name	T337
Test name
Test status
Simulation time	23339819647 ps
CPU time	1480.36 seconds
Started	Jun 13 12:37:37 PM PDT 24
Finished	Jun 13 01:02:18 PM PDT 24
Peak memory	402644 kb
Host	smart-de5484c6-4274-4404-8089-00c442b2a8af
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1082747106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.1082747106 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_224/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_256.293630355
Short name	T1084
Test name
Test status
Simulation time	254764249567 ps
CPU time	1602.75 seconds
Started	Jun 13 12:37:22 PM PDT 24
Finished	Jun 13 01:04:07 PM PDT 24
Peak memory	376628 kb
Host	smart-5e8d40ca-1d8e-4de6-9d7b-13b24d0836c5
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2 56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=293630355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.293630355 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_256/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_384.303855135
Short name	T601
Test name
Test status
Simulation time	301159791772 ps
CPU time	1393.8 seconds
Started	Jun 13 12:37:16 PM PDT 24
Finished	Jun 13 01:00:32 PM PDT 24
Peak memory	331272 kb
Host	smart-759af8f2-5a09-4abe-ac41-8c443de13882
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3 84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=303855135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.303855135 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_384/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_sha3_512.2190180044
Short name	T790
Test name
Test status
Simulation time	137954974789 ps
CPU time	887.28 seconds
Started	Jun 13 12:37:11 PM PDT 24
Finished	Jun 13 12:52:01 PM PDT 24
Peak memory	289564 kb
Host	smart-a6e45a3d-cabc-4105-ac55-5a1e213ad68b
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5 12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2190180044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.2190180044 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_sha3_512/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_128.2250897730
Short name	T280
Test name
Test status
Simulation time	526554813358 ps
CPU time	5469.95 seconds
Started	Jun 13 12:37:12 PM PDT 24
Finished	Jun 13 02:08:25 PM PDT 24
Peak memory	655456 kb
Host	smart-76be9754-be0f-40ef-ab76-b06c97dc7f8f
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2250897730 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.2250897730 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_128/latest

Test location	/workspace/coverage/default/9.kmac_test_vectors_shake_256.1377596208
Short name	T510
Test name
Test status
Simulation time	180944621501 ps
CPU time	3610.24 seconds
Started	Jun 13 12:37:30 PM PDT 24
Finished	Jun 13 01:37:42 PM PDT 24
Peak memory	563980 kb
Host	smart-44f890a7-4b6c-4db7-ac12-abb26caea13e
User	root
Command	/workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant= 256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1377596208 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.1377596208 +enable_masking=0 +sw_key_masked=0
Directory	/workspace/9.kmac_test_vectors_shake_256/latest

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