Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99123947	1			T2	17862		T3	107369		T13	18009
all_values[1]	99123947	1			T2	17862		T3	107369		T13	18009
all_values[2]	99123947	1			T2	17862		T3	107369		T13	18009

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

535711

1

T2

849

T3

3

T13

167

auto[1]

296836130

1

T2

52737

T3

322104

T13

53860

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295843344

1

T2

53115

T3

320997

T13

53499

auto[1]

1528497

1

T2

471

T3

1110

T13

528

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	166630	1			T2	173		T3	1		T13	1
all_values[0]	auto[0]	auto[1]	1971	1			T2	2		T3	2		T14	4
all_values[0]	auto[1]	auto[0]	98447818	1			T2	17532		T3	106998		T13	17832
all_values[0]	auto[1]	auto[1]	507528	1			T2	155		T3	368		T13	176
all_values[1]	auto[0]	auto[0]	186971	1			T2	173		T14	592		T16	6356
all_values[1]	auto[0]	auto[1]	1487	1			T2	2		T14	5		T16	4
all_values[1]	auto[1]	auto[0]	98427477	1			T2	17532		T3	106999		T13	17833
all_values[1]	auto[1]	auto[1]	508012	1			T2	155		T3	370		T13	176
all_values[2]	auto[0]	auto[0]	177079	1			T2	493		T13	165		T14	428
all_values[2]	auto[0]	auto[1]	1573	1			T2	6		T13	1		T14	4
all_values[2]	auto[1]	auto[0]	98437369	1			T2	17212		T3	106999		T13	17668
all_values[2]	auto[1]	auto[1]	507926	1			T2	151		T3	370		T13	175