Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
356332 |
1 |
|
|
T2 |
218 |
|
T3 |
2 |
|
T13 |
368 |
auto[1] |
337274 |
1 |
|
|
T3 |
490 |
|
T14 |
138 |
|
T15 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172782 |
1 |
|
|
T2 |
67 |
|
T3 |
118 |
|
T13 |
91 |
lower_val |
171168 |
1 |
|
|
T2 |
48 |
|
T3 |
132 |
|
T13 |
102 |
zero_val |
1818 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346902 |
1 |
|
|
T2 |
112 |
|
T3 |
208 |
|
T13 |
180 |
lower_val |
346700 |
1 |
|
|
T2 |
106 |
|
T3 |
284 |
|
T13 |
188 |
zero_val |
4 |
1 |
|
|
T170 |
2 |
|
T171 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44936 |
1 |
|
|
T2 |
32 |
|
T13 |
44 |
|
T16 |
6 |
higher_val |
higher_val |
auto[1] |
41569 |
1 |
|
|
T3 |
47 |
|
T14 |
21 |
|
T15 |
1 |
higher_val |
lower_val |
auto[0] |
44369 |
1 |
|
|
T2 |
35 |
|
T13 |
47 |
|
T16 |
8 |
higher_val |
lower_val |
auto[1] |
41906 |
1 |
|
|
T3 |
71 |
|
T14 |
24 |
|
T15 |
1 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T170 |
1 |
|
T171 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43666 |
1 |
|
|
T2 |
29 |
|
T13 |
50 |
|
T14 |
1 |
lower_val |
higher_val |
auto[1] |
41928 |
1 |
|
|
T3 |
61 |
|
T14 |
16 |
|
T15 |
2 |
lower_val |
lower_val |
auto[0] |
43616 |
1 |
|
|
T2 |
19 |
|
T13 |
52 |
|
T16 |
7 |
lower_val |
lower_val |
auto[1] |
41956 |
1 |
|
|
T3 |
71 |
|
T14 |
9 |
|
T15 |
3 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T170 |
1 |
|
T171 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
687 |
1 |
|
|
T13 |
1 |
|
T14 |
1 |
|
T15 |
1 |
zero_val |
higher_val |
auto[1] |
220 |
1 |
|
|
T67 |
1 |
|
T26 |
1 |
|
T172 |
1 |
zero_val |
lower_val |
auto[0] |
685 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
226 |
1 |
|
|
T14 |
2 |
|
T67 |
1 |
|
T26 |
1 |