Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8804	1			T14	3		T16	8		T17	24
len_5001_7500	13998	1			T3	33		T14	13		T16	18
len_2501_5000	9174	1			T3	34		T14	2		T16	3
len_1025_2500	5368	1			T3	20		T14	1		T16	2
len_769_1024	6513	1			T2	32		T3	4		T13	31
len_513_768	6946	1			T2	31		T3	3		T13	28
len_257_512	21435	1			T2	26		T3	4		T13	31
len_0_256	257121	1			T2	20		T3	148		T13	29
len_keccak_block_sizes[72]	725	1			T3	2		T17	2		T18	2
len_keccak_block_sizes[104]	621	1			T17	2		T18	2		T35	3
len_keccak_block_sizes[136]	523	1			T35	3		T36	3		T67	3
len_keccak_block_sizes[144]	430	1			T35	3		T36	3		T67	3
len_keccak_block_sizes[168]	320	1			T35	3		T36	3		T67	3
len_1	754	1			T3	2		T17	2		T18	2
len_0	1162	1			T3	2		T16	1		T17	2