Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99123947	1			T2	17862		T3	107369		T13	18009
all_pins[1]	99123947	1			T2	17862		T3	107369		T13	18009
all_pins[2]	99123947	1			T2	17862		T3	107369		T13	18009

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	296570115	1			T2	53431		T3	321739		T13	53851
values[0x1]	801726	1			T2	155		T3	368		T13	176
transitions[0x0=>0x1]	799947	1			T2	155		T3	368		T13	176
transitions[0x1=>0x0]	799969	1			T2	155		T3	368		T13	176

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98616419	1			T2	17707		T3	107001		T13	17833
all_pins[0]	values[0x1]	507528	1			T2	155		T3	368		T13	176
all_pins[0]	transitions[0x0=>0x1]	507519	1			T2	155		T3	368		T13	176
all_pins[0]	transitions[0x1=>0x0]	61	1			T41	2		T185	8		T186	3
all_pins[1]	values[0x0]	99123877	1			T2	17862		T3	107369		T13	18009
all_pins[1]	values[0x1]	70	1			T41	2		T185	8		T186	3
all_pins[1]	transitions[0x0=>0x1]	60	1			T41	2		T185	8		T186	3
all_pins[1]	transitions[0x1=>0x0]	294118	1			T14	124		T28	291		T29	311
all_pins[2]	values[0x0]	98829819	1			T2	17862		T3	107369		T13	18009
all_pins[2]	values[0x1]	294128	1			T14	124		T28	291		T29	311
all_pins[2]	transitions[0x0=>0x1]	292368	1			T14	122		T28	291		T29	311
all_pins[2]	transitions[0x1=>0x0]	505790	1			T2	155		T3	368		T13	176