Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	665	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5500	1			T2	24		T13	23		T14	10
len_601_800	12559	1			T2	40		T13	35		T14	24
len_401_600	8336	1			T2	15		T13	31		T14	15
len_201_400	16493	1			T2	21		T13	14		T14	13
len_65_200	73551	1			T2	5		T13	9		T14	4
len_min_for_xof_require_squeeze	991	1			T13	1		T35	10		T36	10
len_keccak_block_sizes[72]	747	1			T35	5		T36	5		T67	5
len_keccak_block_sizes[104]	740	1			T35	5		T36	5		T67	5
len_keccak_block_sizes[136]	739	1			T35	5		T36	5		T67	5
len_keccak_block_sizes[144]	284	1			T14	1		T35	5		T36	5
len_keccak_block_sizes[168]	280	1			T35	5		T36	5		T67	5
len_datapath_width	14066	1			T3	246		T15	3		T35	5
len_2_63	214319	1			T2	3		T13	70		T14	5
len_1	52	1			T41	1		T111	2		T157	1