Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10758733 |
1 |
|
|
T2 |
18722 |
|
T3 |
3936 |
|
T13 |
21096 |
auto[1] |
25771969 |
1 |
|
|
T2 |
26866 |
|
T3 |
12300 |
|
T13 |
32914 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36411661 |
1 |
|
|
T2 |
45509 |
|
T3 |
16236 |
|
T13 |
53917 |
triple_byte_access |
39445 |
1 |
|
|
T2 |
33 |
|
T13 |
26 |
|
T14 |
22 |
halfword_access |
40128 |
1 |
|
|
T2 |
25 |
|
T13 |
37 |
|
T14 |
18 |
byte_access |
39468 |
1 |
|
|
T2 |
21 |
|
T13 |
30 |
|
T14 |
13 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10639692 |
1 |
|
|
T2 |
18643 |
|
T3 |
3936 |
|
T13 |
21003 |
auto[0] |
triple_byte_access |
39445 |
1 |
|
|
T2 |
33 |
|
T13 |
26 |
|
T14 |
22 |
auto[0] |
halfword_access |
40128 |
1 |
|
|
T2 |
25 |
|
T13 |
37 |
|
T14 |
18 |
auto[0] |
byte_access |
39468 |
1 |
|
|
T2 |
21 |
|
T13 |
30 |
|
T14 |
13 |
auto[1] |
word_access |
25771969 |
1 |
|
|
T2 |
26866 |
|
T3 |
12300 |
|
T13 |
32914 |