Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 266 1 T133 7 T134 4 T135 7
all_values[1] 266 1 T133 7 T134 4 T135 7
all_values[2] 266 1 T133 7 T134 4 T135 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 448 1 T133 10 T134 7 T135 13
auto[1] 350 1 T133 11 T134 5 T135 8


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 368 1 T133 5 T134 5 T135 7
auto[1] 430 1 T133 16 T134 7 T135 14


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 472 1 T133 10 T134 9 T135 10
auto[1] 326 1 T133 11 T134 3 T135 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 61 1 T133 1 T134 1 T135 1
all_values[0] auto[0] auto[0] auto[1] 29 1 T134 1 T135 1 T180 3
all_values[0] auto[0] auto[1] auto[0] 43 1 T134 1 T135 1 T180 1
all_values[0] auto[0] auto[1] auto[1] 15 1 T133 2 T181 1 T182 1
all_values[0] auto[1] auto[0] auto[1] 66 1 T133 3 T134 1 T135 3
all_values[0] auto[1] auto[1] auto[1] 52 1 T133 1 T135 1 T180 1
all_values[1] auto[0] auto[0] auto[0] 94 1 T133 3 T134 2 T135 3
all_values[1] auto[0] auto[1] auto[0] 65 1 T133 1 T134 1 T180 2
all_values[1] auto[1] auto[0] auto[1] 63 1 T133 1 T134 1 T135 3
all_values[1] auto[1] auto[1] auto[1] 44 1 T133 2 T135 1 T180 1
all_values[2] auto[0] auto[0] auto[0] 57 1 T135 1 T180 1 T183 3
all_values[2] auto[0] auto[0] auto[1] 25 1 T180 1 T181 1 T183 1
all_values[2] auto[0] auto[1] auto[0] 48 1 T135 1 T181 1 T183 1
all_values[2] auto[0] auto[1] auto[1] 35 1 T133 3 T134 3 T135 2
all_values[2] auto[1] auto[0] auto[1] 53 1 T133 2 T134 1 T135 1
all_values[2] auto[1] auto[1] auto[1] 48 1 T133 2 T135 2 T181 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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