Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100228120	1			T1	269		T2	122		T3	2764
all_values[1]	100228120	1			T1	269		T2	122		T3	2764
all_values[2]	100228120	1			T1	269		T2	122		T3	2764

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

644645

1

T1

89

T2

4

T3

196

auto[1]

300039715

1

T1

718

T2

362

T3

8096

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299163780

1

T1

762

T2

366

T3

8211

auto[1]

1520580

1

T1

45

T3

81

T12

1719

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	244007	1			T1	81		T3	192		T13	31
all_values[0]	auto[0]	auto[1]	2054	1			T1	8		T3	4		T13	6
all_values[0]	auto[1]	auto[0]	99477253	1			T1	173		T2	122		T3	2545
all_values[0]	auto[1]	auto[1]	504806	1			T1	7		T3	23		T12	573
all_values[1]	auto[0]	auto[0]	190788	1			T2	3		T12	9		T14	4
all_values[1]	auto[0]	auto[1]	1541	1			T12	3		T14	2		T15	1
all_values[1]	auto[1]	auto[0]	99530472	1			T1	254		T2	119		T3	2737
all_values[1]	auto[1]	auto[1]	505319	1			T1	15		T3	27		T12	570
all_values[2]	auto[0]	auto[0]	204711	1			T2	1		T12	5		T13	23
all_values[2]	auto[0]	auto[1]	1544	1			T12	2		T13	4		T14	3
all_values[2]	auto[1]	auto[0]	99516549	1			T1	254		T2	121		T3	2737
all_values[2]	auto[1]	auto[1]	505316	1			T1	15		T3	27		T12	571