Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
357666 |
1 |
|
|
T1 |
18 |
|
T2 |
2 |
|
T3 |
38 |
auto[1] |
330720 |
1 |
|
|
T2 |
240 |
|
T18 |
746 |
|
T52 |
46 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172101 |
1 |
|
|
T1 |
2 |
|
T2 |
46 |
|
T3 |
10 |
lower_val |
171539 |
1 |
|
|
T1 |
3 |
|
T2 |
44 |
|
T3 |
9 |
zero_val |
1798 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
343914 |
1 |
|
|
T1 |
8 |
|
T2 |
122 |
|
T3 |
26 |
lower_val |
344468 |
1 |
|
|
T1 |
10 |
|
T2 |
120 |
|
T3 |
12 |
zero_val |
4 |
1 |
|
|
T163 |
2 |
|
T164 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
5 |
13 |
72.22 |
5 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
* |
-- |
-- |
4 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
44451 |
1 |
|
|
T1 |
1 |
|
T3 |
6 |
|
T12 |
78 |
higher_val |
higher_val |
auto[1] |
41397 |
1 |
|
|
T2 |
31 |
|
T18 |
83 |
|
T52 |
9 |
higher_val |
lower_val |
auto[0] |
44845 |
1 |
|
|
T1 |
1 |
|
T3 |
4 |
|
T12 |
96 |
higher_val |
lower_val |
auto[1] |
41407 |
1 |
|
|
T2 |
15 |
|
T18 |
87 |
|
T52 |
5 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T164 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
44615 |
1 |
|
|
T1 |
1 |
|
T3 |
5 |
|
T12 |
92 |
lower_val |
higher_val |
auto[1] |
41144 |
1 |
|
|
T2 |
19 |
|
T18 |
93 |
|
T52 |
6 |
lower_val |
lower_val |
auto[0] |
44601 |
1 |
|
|
T1 |
2 |
|
T3 |
4 |
|
T12 |
98 |
lower_val |
lower_val |
auto[1] |
41179 |
1 |
|
|
T2 |
25 |
|
T18 |
93 |
|
T52 |
1 |
zero_val |
higher_val |
auto[0] |
709 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T13 |
2 |
zero_val |
higher_val |
auto[1] |
219 |
1 |
|
|
T60 |
3 |
|
T61 |
1 |
|
T63 |
2 |
zero_val |
lower_val |
auto[0] |
670 |
1 |
|
|
T2 |
1 |
|
T12 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
200 |
1 |
|
|
T60 |
3 |
|
T61 |
1 |
|
T63 |
2 |