Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::error_cg

Group : kmac_env_pkg::kmac_env_cov::error_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
89.66	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::error_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	21	3	18	85.71
Crosses	8	0	8	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::error_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cmd	4	0	4	100.00	100	1	1	0
kmac_err_code	9	3	6	66.67	100	1	1	0
mode	3	0	3	100.00	100	1	1	0
strength	5	0	5	100.00	100	1	1	0

Crosses for Group kmac_env_pkg::kmac_env_cov::error_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_invalid_cmd_in_app_active	1	0	1	100.00	100	1	1	0
all_invalid_mode_strength_cfgs	7	0	7	100.00	100	1	1	0

Summary for Variable cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cmd

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[CmdNone]	0	Excluded
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[CmdStart]	603	1			T30	21		T32	17		T38	10
auto[CmdProcess]	97	1			T30	4		T31	1		T32	3
auto[CmdManualRun]	316	1			T30	16		T31	4		T32	11
auto[CmdDone]	1148	1			T3	2		T30	42		T31	2

---

Summary for Variable kmac_err_code

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	9	3	6	66.67

Automatically Generated Bins for kmac_err_code

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ErrFatalError]	0	1	1
auto[ErrPackerIntegrity]	0	1	1
auto[ErrMsgFifoIntegrity]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[ErrNone]	0	Excluded
auto[ErrWaitTimerExpired]	0	Illegal
auto[ErrIncorrectEntropyMode]	0	Illegal
auto[ErrSwHashingWithoutEntropyReady]	0	Illegal
auto[ErrShadowRegUpdate]	0	Illegal
il	0	Illegal
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ErrKeyNotValid]	50	1			T16	1		T20	1		T21	1
auto[ErrSwPushedMsgFifo]	40	1			T3	1		T30	1		T32	2
auto[ErrSwIssuedCmdInAppActive]	42	1			T30	1		T31	1		T32	1
auto[ErrUnexpectedModeStrength]	508	1			T30	20		T31	1		T32	19
auto[ErrIncorrectFunctionName]	500	1			T30	20		T32	15		T38	9
auto[ErrSwCmdSequence]	1097	1			T3	1		T30	41		T31	5

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	313	1			T30	11		T31	1		T32	18
auto[Shake]	358	1			T30	21		T31	1		T32	11
auto[CShake]	1516	1			T3	2		T30	51		T31	5

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	761	1			T3	1		T30	33		T31	1
auto[L224]	257	1			T30	3		T32	8		T38	3
auto[L256]	759	1			T3	1		T16	1		T30	27
auto[L384]	194	1			T30	11		T32	8		T38	7
auto[L512]	266	1			T30	9		T32	8		T38	2

---

Summary for Cross all_invalid_cmd_in_app_active

Samples crossed: kmac_err_code cmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for all_invalid_cmd_in_app_active

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

invalid_cmds

42

1

T30

1

T31

1

T32

1

---

Summary for Cross all_invalid_mode_strength_cfgs

Samples crossed: kmac_err_code mode strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	7	0	7	100.00

User Defined Cross Bins for all_invalid_mode_strength_cfgs

Excluded/Illegal bins

NAME	COUNT	STATUS
ignore	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha3_128_cfgs	149	1			T30	7		T31	1		T32	7
shake_224_invalid_cfg	29	1			T32	1		T170	1		T33	1
shake_384_invalid_cfg	25	1			T30	2		T38	1		T26	1
shake_512_invalid_cfg	35	1			T30	1		T32	2		T38	1
cshake_224_invalid_cfg	96	1			T30	1		T32	3		T38	1
cshake_384_invalid_cfg	77	1			T30	5		T32	4		T38	2
cshake_512_invalid_cfg	97	1			T30	4		T32	2		T38	1