Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100228120	1			T1	269		T2	122		T3	2764
all_pins[1]	100228120	1			T1	269		T2	122		T3	2764
all_pins[2]	100228120	1			T1	269		T2	122		T3	2764

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299891371	1			T1	800		T2	366		T3	8267
values[0x1]	792989	1			T1	7		T3	25		T12	573
transitions[0x0=>0x1]	791192	1			T1	7		T3	25		T12	573
transitions[0x1=>0x0]	791217	1			T1	7		T3	25		T12	573

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99723314	1			T1	262		T2	122		T3	2741
all_pins[0]	values[0x1]	504806	1			T1	7		T3	23		T12	573
all_pins[0]	transitions[0x0=>0x1]	504792	1			T1	7		T3	23		T12	573
all_pins[0]	transitions[0x1=>0x0]	53	1			T175	7		T176	3		T177	2
all_pins[1]	values[0x0]	100228053	1			T1	269		T2	122		T3	2764
all_pins[1]	values[0x1]	67	1			T175	7		T176	3		T177	2
all_pins[1]	transitions[0x0=>0x1]	49	1			T175	7		T176	3		T177	2
all_pins[1]	transitions[0x1=>0x0]	288098	1			T3	2		T30	966		T31	7
all_pins[2]	values[0x0]	99940004	1			T1	269		T2	122		T3	2762
all_pins[2]	values[0x1]	288116	1			T3	2		T30	966		T31	7
all_pins[2]	transitions[0x0=>0x1]	286351	1			T3	2		T30	966		T31	7
all_pins[2]	transitions[0x1=>0x0]	503066	1			T1	7		T3	23		T12	573