Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::sideload_cg

Group : kmac_env_pkg::kmac_env_cov::sideload_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::sideload_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
in_app_keymgr	2	0	2	100.00	100	1	1	2
kmac_mode	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::kmac_env_cov::sideload_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_cross	4	0	4	100.00	100	1	1	0

Summary for Variable in_app_keymgr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for in_app_keymgr

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

337750

1

T1

9

T2

178

T3

18

auto[1]

3113

1

T2

64

T16

1

T22

17

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Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305827

1

T2

114

T3

8

T12

360

auto[1]

35036

1

T1

9

T2

128

T3

10

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Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327678

1

T1

9

T2

161

T3

16

auto[1]

13185

1

T2

81

T3

2

T16

1

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Summary for Cross sideload_cross

Samples crossed: sideload kmac_mode in_app_keymgr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	4	0	4	100.00

User Defined Cross Bins for sideload_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_kmac_valid_sideload	13185	1			T2	81		T3	2		T16	1
sw_kmac_invalid_sideload	327678	1			T1	9		T2	161		T3	16
app_valid_sideload	13185	1			T2	81		T3	2		T16	1
app_invalid_sideload	327678	1			T1	9		T2	161		T3	16