Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10390084 |
1 |
|
|
T1 |
96 |
|
T2 |
3636 |
|
T3 |
3134 |
auto[1] |
25209678 |
1 |
|
|
T1 |
450 |
|
T2 |
8234 |
|
T3 |
4630 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35482250 |
1 |
|
|
T1 |
546 |
|
T2 |
11870 |
|
T3 |
7748 |
triple_byte_access |
39070 |
1 |
|
|
T3 |
8 |
|
T13 |
30 |
|
T15 |
279 |
halfword_access |
39387 |
1 |
|
|
T3 |
2 |
|
T13 |
23 |
|
T15 |
279 |
byte_access |
39055 |
1 |
|
|
T3 |
6 |
|
T13 |
25 |
|
T15 |
279 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10272572 |
1 |
|
|
T1 |
96 |
|
T2 |
3636 |
|
T3 |
3118 |
auto[0] |
triple_byte_access |
39070 |
1 |
|
|
T3 |
8 |
|
T13 |
30 |
|
T15 |
279 |
auto[0] |
halfword_access |
39387 |
1 |
|
|
T3 |
2 |
|
T13 |
23 |
|
T15 |
279 |
auto[0] |
byte_access |
39055 |
1 |
|
|
T3 |
6 |
|
T13 |
25 |
|
T15 |
279 |
auto[1] |
word_access |
25209678 |
1 |
|
|
T1 |
450 |
|
T2 |
8234 |
|
T3 |
4630 |