Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100623257	1			T1	274		T2	86213		T3	17007
all_values[1]	100623257	1			T1	274		T2	86213		T3	17007
all_values[2]	100623257	1			T1	274		T2	86213		T3	17007

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

480281

1

T1

128

T2

7

T3

403

auto[1]

301389490

1

T1

694

T2

258632

T3

50618

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300347802

1

T1

756

T2

257997

T3

50511

auto[1]

1521969

1

T1

66

T2

642

T3

510

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162784	1			T1	72		T13	6		T16	3
all_values[0]	auto[0]	auto[1]	1901	1			T1	6		T13	6		T16	4
all_values[0]	auto[1]	auto[0]	99953150	1			T1	180		T2	85999		T3	16837
all_values[0]	auto[1]	auto[1]	505422	1			T1	16		T2	214		T3	170
all_values[1]	auto[0]	auto[0]	169642	1			T1	46		T3	60		T13	3
all_values[1]	auto[0]	auto[1]	1414	1			T1	4		T3	1		T13	4
all_values[1]	auto[1]	auto[0]	99946292	1			T1	206		T2	85999		T3	16777
all_values[1]	auto[1]	auto[1]	505909	1			T1	18		T2	214		T3	169
all_values[2]	auto[0]	auto[0]	143092	1			T2	6		T3	337		T13	1
all_values[2]	auto[0]	auto[1]	1448	1			T2	1		T3	5		T13	2
all_values[2]	auto[1]	auto[0]	99972842	1			T1	252		T2	85993		T3	16500
all_values[2]	auto[1]	auto[1]	505875	1			T1	22		T2	213		T3	165