Group : kmac_env_pkg::config_unmasked_cg
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Group : kmac_env_pkg::config_unmasked_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv


Summary for Group kmac_env_pkg::config_unmasked_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 23 0 23 100.00
Crosses 4 0 4 100.00


Variables for Group kmac_env_pkg::config_unmasked_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
key_len 5 0 5 100.00 100 1 1 0
kmac_en 2 0 2 100.00 100 1 1 2
mode 3 0 3 100.00 100 1 1 0
msg_endian 2 0 2 100.00 100 1 1 2
sideload 2 0 2 100.00 100 1 1 2
state_endian 2 0 2 100.00 100 1 1 2
strength 5 0 5 100.00 100 1 1 0
xof_en 2 0 2 100.00 100 1 1 2


Crosses for Group kmac_env_pkg::config_unmasked_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
kmac_cross 1 0 1 100.00 100 1 1 0
cshake_cross 1 0 1 100.00 100 1 1 0
shake_cross 1 0 1 100.00 100 1 1 0
sha3_cross 1 0 1 100.00 100 1 1 0


Summary for Variable key_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for key_len

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[Key128] 66121 1 T1 3 T2 22 T3 23
auto[Key192] 66161 1 T1 3 T2 21 T3 21
auto[Key256] 80235 1 T1 4 T2 46 T3 70
auto[Key384] 65899 1 T1 1 T2 27 T3 37
auto[Key512] 65619 1 T1 2 T2 21 T3 28


Summary for Variable kmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 312173 1 T1 1 T2 30 T3 93
auto[1] 31862 1 T1 12 T2 107 T3 86


Summary for Variable mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 0 3 100.00


Automatically Generated Bins for mode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[Sha3] 67271 1 T2 7 T13 246 T14 1
auto[Shake] 241481 1 T1 1 T2 22 T3 55
auto[CShake] 35283 1 T1 12 T2 108 T3 124


Summary for Variable msg_endian

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for msg_endian

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 171579 1 T1 10 T2 77 T3 91
auto[1] 172456 1 T1 3 T2 60 T3 88


Summary for Variable sideload

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sideload

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 334598 1 T1 13 T2 136 T3 155
auto[1] 9437 1 T2 1 T3 24 T17 4


Summary for Variable state_endian

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for state_endian

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 171602 1 T1 6 T2 69 T3 86
auto[1] 172433 1 T1 7 T2 68 T3 93


Summary for Variable strength

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for strength

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[L128] 138348 1 T1 5 T2 70 T3 79
auto[L224] 19833 1 T2 1 T29 1 T93 4
auto[L256] 157434 1 T1 8 T2 61 T3 100
auto[L384] 15816 1 T2 4 T66 310 T26 1
auto[L512] 12604 1 T2 1 T13 246 T14 1


Summary for Variable xof_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for xof_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 326157 1 T1 3 T2 52 T3 154
auto[1] 17878 1 T1 10 T2 85 T3 25


Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for kmac_cross

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 31862 1 T1 12 T2 107 T3 86


Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for cshake_cross

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 35283 1 T1 12 T2 108 T3 124


Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for shake_cross

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 241481 1 T1 1 T2 22 T3 55


Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
User Defined Cross Bins 1 0 1 100.00


User Defined Cross Bins for sha3_cross

Excluded/Illegal bins
NAME   COUNT   STATUS   
invalid_mode 0 Excluded
invalid_strength 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid 67271 1 T2 7 T13 246 T14 1