Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
330412 |
1 |
|
|
T1 |
26 |
|
T2 |
88 |
|
T3 |
358 |
auto[1] |
359978 |
1 |
|
|
T2 |
186 |
|
T17 |
126 |
|
T18 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173446 |
1 |
|
|
T1 |
5 |
|
T2 |
66 |
|
T3 |
98 |
lower_val |
169874 |
1 |
|
|
T1 |
8 |
|
T2 |
56 |
|
T3 |
78 |
zero_val |
1793 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
344810 |
1 |
|
|
T1 |
8 |
|
T2 |
132 |
|
T3 |
160 |
lower_val |
345560 |
1 |
|
|
T1 |
18 |
|
T2 |
142 |
|
T3 |
198 |
zero_val |
20 |
1 |
|
|
T163 |
2 |
|
T95 |
2 |
|
T164 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41524 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T3 |
43 |
higher_val |
higher_val |
auto[1] |
45395 |
1 |
|
|
T2 |
22 |
|
T17 |
13 |
|
T18 |
562 |
higher_val |
lower_val |
auto[0] |
41222 |
1 |
|
|
T1 |
3 |
|
T2 |
8 |
|
T3 |
55 |
higher_val |
lower_val |
auto[1] |
45293 |
1 |
|
|
T2 |
26 |
|
T17 |
20 |
|
T18 |
562 |
higher_val |
zero_val |
auto[0] |
5 |
1 |
|
|
T164 |
2 |
|
T165 |
1 |
|
T166 |
1 |
higher_val |
zero_val |
auto[1] |
7 |
1 |
|
|
T163 |
2 |
|
T95 |
2 |
|
T167 |
1 |
lower_val |
higher_val |
auto[0] |
40459 |
1 |
|
|
T1 |
2 |
|
T2 |
10 |
|
T3 |
43 |
lower_val |
higher_val |
auto[1] |
44123 |
1 |
|
|
T2 |
14 |
|
T17 |
14 |
|
T18 |
519 |
lower_val |
lower_val |
auto[0] |
40654 |
1 |
|
|
T1 |
6 |
|
T2 |
8 |
|
T3 |
35 |
lower_val |
lower_val |
auto[1] |
44634 |
1 |
|
|
T2 |
24 |
|
T17 |
22 |
|
T18 |
595 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T168 |
2 |
|
T169 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T167 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
647 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
2 |
zero_val |
higher_val |
auto[1] |
247 |
1 |
|
|
T2 |
2 |
|
T170 |
1 |
|
T24 |
1 |
zero_val |
lower_val |
auto[0] |
676 |
1 |
|
|
T1 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
223 |
1 |
|
|
T2 |
1 |
|
T38 |
4 |
|
T170 |
1 |