Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100623257	1			T1	274		T2	86213		T3	17007
all_pins[1]	100623257	1			T1	274		T2	86213		T3	17007
all_pins[2]	100623257	1			T1	274		T2	86213		T3	17007

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301054116	1			T1	806		T2	258425		T3	50851
values[0x1]	815655	1			T1	16		T2	214		T3	170
transitions[0x0=>0x1]	813727	1			T1	16		T2	214		T3	170
transitions[0x1=>0x0]	813754	1			T1	16		T2	214		T3	170

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100117835	1			T1	258		T2	85999		T3	16837
all_pins[0]	values[0x1]	505422	1			T1	16		T2	214		T3	170
all_pins[0]	transitions[0x0=>0x1]	505404	1			T1	16		T2	214		T3	170
all_pins[0]	transitions[0x1=>0x0]	71	1			T152	3		T42	3		T176	3
all_pins[1]	values[0x0]	100623168	1			T1	274		T2	86213		T3	17007
all_pins[1]	values[0x1]	89	1			T152	3		T42	3		T176	3
all_pins[1]	transitions[0x0=>0x1]	70	1			T152	3		T42	3		T176	3
all_pins[1]	transitions[0x1=>0x0]	310125	1			T17	934		T29	206		T23	17987
all_pins[2]	values[0x0]	100313113	1			T1	274		T2	86213		T3	17007
all_pins[2]	values[0x1]	310144	1			T17	934		T29	206		T23	17987
all_pins[2]	transitions[0x0=>0x1]	308253	1			T17	933		T29	205		T23	17858
all_pins[2]	transitions[0x1=>0x0]	503558	1			T1	16		T2	214		T3	170