Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	679	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5271	1			T1	2		T2	14		T3	24
len_601_800	11926	1			T1	7		T2	15		T3	30
len_401_600	7795	1			T1	4		T2	19		T3	32
len_201_400	16279	1			T2	14		T3	15		T17	7
len_65_200	73467	1			T2	28		T3	9		T14	3
len_min_for_xof_require_squeeze	1000	1			T16	9		T18	10		T38	9
len_keccak_block_sizes[72]	750	1			T16	9		T18	5		T38	9
len_keccak_block_sizes[104]	751	1			T16	9		T18	5		T38	9
len_keccak_block_sizes[136]	765	1			T2	1		T16	9		T18	5
len_keccak_block_sizes[144]	280	1			T18	5		T87	5		T184	5
len_keccak_block_sizes[168]	278	1			T3	1		T18	5		T87	5
len_datapath_width	14055	1			T2	7		T13	246		T14	1
len_2_63	214505	1			T2	38		T3	66		T14	4
len_1	58	1			T2	2		T145	1		T24	1