Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100398838	1			T1	464114		T2	159850		T3	454403
all_values[1]	100398838	1			T1	464114		T2	159850		T3	454403
all_values[2]	100398838	1			T1	464114		T2	159850		T3	454403

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

474937

1

T1

9

T2

17

T3

3

auto[1]

300721577

1

T1

139233

T2

479533

T3

136320

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299668464

1

T1

138220

T2

478152

T3

135306

auto[1]

1528050

1

T1

10140

T2

1398

T3

10149

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162236	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	1996	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	99727252	1			T1	460733		T2	159383		T3	451019
all_values[0]	auto[1]	auto[1]	507354	1			T1	3378		T2	464		T3	3381
all_values[1]	auto[0]	auto[0]	129394	1			T1	1		T2	4		T14	4
all_values[1]	auto[0]	auto[1]	1551	1			T1	2		T2	3		T14	3
all_values[1]	auto[1]	auto[0]	99760094	1			T1	460733		T2	159380		T3	451020
all_values[1]	auto[1]	auto[1]	507799	1			T1	3378		T2	463		T3	3383
all_values[2]	auto[0]	auto[0]	178196	1			T1	1		T2	4		T15	1619
all_values[2]	auto[0]	auto[1]	1564	1			T1	2		T2	3		T15	1
all_values[2]	auto[1]	auto[0]	99711292	1			T1	460733		T2	159380		T3	451020
all_values[2]	auto[1]	auto[1]	507786	1			T1	3378		T2	463		T3	3383