Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337488 |
1 |
|
|
T1 |
2 |
|
T2 |
620 |
|
T3 |
4530 |
auto[1] |
356174 |
1 |
|
|
T1 |
4528 |
|
T13 |
490 |
|
T17 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173440 |
1 |
|
|
T1 |
1102 |
|
T2 |
166 |
|
T3 |
1187 |
lower_val |
172262 |
1 |
|
|
T1 |
1171 |
|
T2 |
148 |
|
T3 |
1108 |
zero_val |
1676 |
1 |
|
|
T1 |
5 |
|
T2 |
1 |
|
T3 |
7 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346870 |
1 |
|
|
T1 |
2234 |
|
T2 |
324 |
|
T3 |
2174 |
lower_val |
346780 |
1 |
|
|
T1 |
2296 |
|
T2 |
296 |
|
T3 |
2356 |
zero_val |
12 |
1 |
|
|
T150 |
2 |
|
T151 |
2 |
|
T152 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41907 |
1 |
|
|
T2 |
84 |
|
T3 |
560 |
|
T14 |
103 |
higher_val |
higher_val |
auto[1] |
44987 |
1 |
|
|
T1 |
552 |
|
T13 |
64 |
|
T17 |
525 |
higher_val |
lower_val |
auto[0] |
41874 |
1 |
|
|
T2 |
82 |
|
T3 |
627 |
|
T14 |
105 |
higher_val |
lower_val |
auto[1] |
44668 |
1 |
|
|
T1 |
550 |
|
T13 |
68 |
|
T17 |
569 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T153 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T152 |
1 |
|
T154 |
1 |
|
T155 |
1 |
lower_val |
higher_val |
auto[0] |
42025 |
1 |
|
|
T2 |
70 |
|
T3 |
552 |
|
T14 |
77 |
lower_val |
higher_val |
auto[1] |
44134 |
1 |
|
|
T1 |
535 |
|
T13 |
43 |
|
T17 |
541 |
lower_val |
lower_val |
auto[0] |
42077 |
1 |
|
|
T2 |
78 |
|
T3 |
556 |
|
T14 |
90 |
lower_val |
lower_val |
auto[1] |
44022 |
1 |
|
|
T1 |
636 |
|
T13 |
72 |
|
T17 |
576 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T151 |
2 |
|
T155 |
1 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
612 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
192 |
1 |
|
|
T1 |
2 |
|
T17 |
5 |
|
T37 |
2 |
zero_val |
lower_val |
auto[0] |
664 |
1 |
|
|
T1 |
1 |
|
T3 |
2 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
208 |
1 |
|
|
T1 |
2 |
|
T13 |
2 |
|
T17 |
3 |