Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100398838	1			T1	464114		T2	159850		T3	454403
all_pins[1]	100398838	1			T1	464114		T2	159850		T3	454403
all_pins[2]	100398838	1			T1	464114		T2	159850		T3	454403

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300359822	1			T1	138896		T2	479086		T3	135982
values[0x1]	836692	1			T1	3378		T2	464		T3	3381
transitions[0x0=>0x1]	834738	1			T1	3378		T2	464		T3	3381
transitions[0x1=>0x0]	834763	1			T1	3378		T2	464		T3	3381

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99891484	1			T1	460736		T2	159386		T3	451022
all_pins[0]	values[0x1]	507354	1			T1	3378		T2	464		T3	3381
all_pins[0]	transitions[0x0=>0x1]	507342	1			T1	3378		T2	464		T3	3381
all_pins[0]	transitions[0x1=>0x0]	60	1			T25	2		T43	3		T160	3
all_pins[1]	values[0x0]	100398766	1			T1	464114		T2	159850		T3	454403
all_pins[1]	values[0x1]	72	1			T25	2		T43	3		T160	3
all_pins[1]	transitions[0x0=>0x1]	65	1			T25	2		T43	3		T160	3
all_pins[1]	transitions[0x1=>0x0]	329259	1			T24	15734		T25	8920		T28	701
all_pins[2]	values[0x0]	100069572	1			T1	464114		T2	159850		T3	454403
all_pins[2]	values[0x1]	329266	1			T24	15734		T25	8920		T28	701
all_pins[2]	transitions[0x0=>0x1]	327331	1			T24	15639		T25	8862		T28	700
all_pins[2]	transitions[0x1=>0x0]	505444	1			T1	3378		T2	464		T3	3381