Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	658	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5430	1			T15	19		T16	6		T19	20
len_601_800	12488	1			T15	35		T16	9		T19	49
len_401_600	8254	1			T15	28		T16	11		T19	29
len_201_400	16412	1			T1	251		T3	251		T15	9
len_65_200	73717	1			T1	680		T3	680		T15	11
len_min_for_xof_require_squeeze	1008	1			T1	10		T3	10		T17	10
len_keccak_block_sizes[72]	773	1			T1	5		T3	5		T15	1
len_keccak_block_sizes[104]	757	1			T1	5		T3	5		T17	5
len_keccak_block_sizes[136]	739	1			T1	5		T3	5		T17	5
len_keccak_block_sizes[144]	278	1			T1	5		T3	5		T17	5
len_keccak_block_sizes[168]	288	1			T1	5		T3	5		T17	5
len_datapath_width	14027	1			T1	5		T3	5		T13	246
len_2_63	214600	1			T1	1329		T2	310		T3	1329
len_1	54	1			T169	2		T170	1		T171	1