Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 290 1 T118 7 T120 7 T156 7
all_values[1] 290 1 T118 7 T120 7 T156 7
all_values[2] 290 1 T118 7 T120 7 T156 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 486 1 T118 13 T120 9 T156 12
auto[1] 384 1 T118 8 T120 12 T156 9


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 404 1 T118 10 T120 13 T156 5
auto[1] 466 1 T118 11 T120 8 T156 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 518 1 T118 13 T120 15 T156 12
auto[1] 352 1 T118 8 T120 6 T156 9


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 63 1 T118 5 T120 1 T157 2
all_values[0] auto[0] auto[0] auto[1] 35 1 T120 1 T156 2 T157 1
all_values[0] auto[0] auto[1] auto[0] 51 1 T120 3 T157 1 T158 1
all_values[0] auto[0] auto[1] auto[1] 25 1 T118 1 T156 1 T158 2
all_values[0] auto[1] auto[0] auto[1] 64 1 T120 1 T156 3 T157 3
all_values[0] auto[1] auto[1] auto[1] 52 1 T118 1 T120 1 T156 1
all_values[1] auto[0] auto[0] auto[0] 94 1 T118 1 T120 2 T156 2
all_values[1] auto[0] auto[1] auto[0] 74 1 T118 1 T120 2 T156 3
all_values[1] auto[1] auto[0] auto[1] 66 1 T118 3 T120 1 T156 1
all_values[1] auto[1] auto[1] auto[1] 56 1 T118 2 T120 2 T156 1
all_values[2] auto[0] auto[0] auto[0] 66 1 T118 1 T120 2 T157 3
all_values[2] auto[0] auto[0] auto[1] 34 1 T118 1 T120 1 T156 2
all_values[2] auto[0] auto[1] auto[0] 56 1 T118 2 T120 3 T159 1
all_values[2] auto[0] auto[1] auto[1] 20 1 T118 1 T156 2 T159 1
all_values[2] auto[1] auto[0] auto[1] 64 1 T118 2 T156 2 T157 3
all_values[2] auto[1] auto[1] auto[1] 50 1 T120 1 T156 1 T159 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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