Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100709281	1			T1	116128		T2	218233		T3	1006
all_values[1]	100709281	1			T1	116128		T2	218233		T3	1006
all_values[2]	100709281	1			T1	116128		T2	218233		T3	1006

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567387

1

T1

4993

T2

41

T3

20

auto[1]

301560456

1

T1

343391

T2

654658

T3

2998

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300592188

1

T1

348045

T2

652929

T3

2775

auto[1]

1535655

1

T1

339

T2

1770

T3

243

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162833	1			T16	1		T36	3		T37	1
all_values[0]	auto[0]	auto[1]	1934	1			T16	2		T36	4		T37	2
all_values[0]	auto[1]	auto[0]	100034563	1			T1	116015		T2	217643		T3	925
all_values[0]	auto[1]	auto[1]	509951	1			T1	113		T2	590		T3	81
all_values[1]	auto[0]	auto[0]	201753	1			T1	1305		T2	29		T3	12
all_values[1]	auto[0]	auto[1]	1675	1			T1	1		T2	12		T3	2
all_values[1]	auto[1]	auto[0]	99995643	1			T1	114710		T2	217614		T3	913
all_values[1]	auto[1]	auto[1]	510210	1			T1	112		T2	578		T3	79
all_values[2]	auto[0]	auto[0]	197526	1			T1	3685		T3	5		T13	6
all_values[2]	auto[0]	auto[1]	1666	1			T1	2		T3	1		T13	5
all_values[2]	auto[1]	auto[0]	99999870	1			T1	112330		T2	217643		T3	920
all_values[2]	auto[1]	auto[1]	510219	1			T1	111		T2	590		T3	80