Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
383768 |
1 |
|
|
T1 |
2 |
|
T2 |
780 |
|
T3 |
2 |
auto[1] |
313204 |
1 |
|
|
T1 |
146 |
|
T3 |
112 |
|
T13 |
4528 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175103 |
1 |
|
|
T1 |
38 |
|
T2 |
176 |
|
T3 |
30 |
lower_val |
172442 |
1 |
|
|
T1 |
40 |
|
T2 |
202 |
|
T3 |
36 |
zero_val |
1819 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348710 |
1 |
|
|
T1 |
74 |
|
T2 |
370 |
|
T3 |
56 |
lower_val |
348250 |
1 |
|
|
T1 |
74 |
|
T2 |
410 |
|
T3 |
58 |
zero_val |
12 |
1 |
|
|
T93 |
2 |
|
T180 |
2 |
|
T181 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47972 |
1 |
|
|
T2 |
94 |
|
T14 |
29 |
|
T15 |
39 |
higher_val |
higher_val |
auto[1] |
39193 |
1 |
|
|
T1 |
23 |
|
T3 |
13 |
|
T13 |
594 |
higher_val |
lower_val |
auto[0] |
48201 |
1 |
|
|
T2 |
82 |
|
T14 |
36 |
|
T15 |
43 |
higher_val |
lower_val |
auto[1] |
39732 |
1 |
|
|
T1 |
15 |
|
T3 |
17 |
|
T13 |
593 |
higher_val |
zero_val |
auto[0] |
5 |
1 |
|
|
T93 |
1 |
|
T180 |
1 |
|
T182 |
1 |
lower_val |
higher_val |
auto[0] |
47497 |
1 |
|
|
T2 |
90 |
|
T14 |
38 |
|
T15 |
28 |
lower_val |
higher_val |
auto[1] |
38910 |
1 |
|
|
T1 |
17 |
|
T3 |
19 |
|
T13 |
496 |
lower_val |
lower_val |
auto[0] |
47136 |
1 |
|
|
T2 |
112 |
|
T14 |
30 |
|
T15 |
34 |
lower_val |
lower_val |
auto[1] |
38895 |
1 |
|
|
T1 |
23 |
|
T3 |
17 |
|
T13 |
502 |
lower_val |
zero_val |
auto[0] |
4 |
1 |
|
|
T180 |
1 |
|
T181 |
1 |
|
T183 |
1 |
zero_val |
higher_val |
auto[0] |
692 |
1 |
|
|
T15 |
1 |
|
T19 |
1 |
|
T35 |
1 |
zero_val |
higher_val |
auto[1] |
208 |
1 |
|
|
T13 |
2 |
|
T184 |
2 |
|
T24 |
4 |
zero_val |
lower_val |
auto[0] |
699 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
220 |
1 |
|
|
T13 |
2 |
|
T184 |
2 |
|
T24 |
2 |