Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100709281	1			T1	116128		T2	218233		T3	1006
all_pins[1]	100709281	1			T1	116128		T2	218233		T3	1006
all_pins[2]	100709281	1			T1	116128		T2	218233		T3	1006

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301270861	1			T1	348271		T2	654109		T3	2937
values[0x1]	856982	1			T1	113		T2	590		T3	81
transitions[0x0=>0x1]	854795	1			T1	113		T2	590		T3	81
transitions[0x1=>0x0]	854809	1			T1	113		T2	590		T3	81

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100199330	1			T1	116015		T2	217643		T3	925
all_pins[0]	values[0x1]	509951	1			T1	113		T2	590		T3	81
all_pins[0]	transitions[0x0=>0x1]	509937	1			T1	113		T2	590		T3	81
all_pins[0]	transitions[0x1=>0x0]	64	1			T42	3		T43	2		T44	4
all_pins[1]	values[0x0]	100709203	1			T1	116128		T2	218233		T3	1006
all_pins[1]	values[0x1]	78	1			T42	3		T43	2		T44	4
all_pins[1]	transitions[0x0=>0x1]	66	1			T42	3		T43	2		T44	4
all_pins[1]	transitions[0x1=>0x0]	346941	1			T24	4745		T29	240		T25	9003
all_pins[2]	values[0x0]	100362328	1			T1	116128		T2	218233		T3	1006
all_pins[2]	values[0x1]	346953	1			T24	4745		T29	240		T25	9003
all_pins[2]	transitions[0x0=>0x1]	344792	1			T24	4712		T29	240		T25	8940
all_pins[2]	transitions[0x1=>0x0]	507804	1			T1	113		T2	590		T3	81