Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	98879321	1			T1	62023		T2	459203		T3	464830
all_values[1]	98879321	1			T1	62023		T2	459203		T3	464830
all_values[2]	98879321	1			T1	62023		T2	459203		T3	464830

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

550274

1

T1

1847

T2

3

T3

19

auto[1]

296087689

1

T1

184222

T2

137760

T3

139447

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295116075

1

T1

185805

T2

136745

T3

138418

auto[1]

1521888

1

T1

264

T2

10152

T3

10305

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	146669	1			T1	40		T2	1		T14	583
all_values[0]	auto[0]	auto[1]	1844	1			T1	8		T2	2		T14	2
all_values[0]	auto[1]	auto[0]	98225356	1			T1	61895		T2	455818		T3	461395
all_values[0]	auto[1]	auto[1]	505452	1			T1	80		T2	3382		T3	3435
all_values[1]	auto[0]	auto[0]	186430	1			T1	25		T13	7		T14	583
all_values[1]	auto[0]	auto[1]	1621	1			T1	4		T13	1		T14	2
all_values[1]	auto[1]	auto[0]	98185595	1			T1	61910		T2	455819		T3	461395
all_values[1]	auto[1]	auto[1]	505675	1			T1	84		T2	3384		T3	3435
all_values[2]	auto[0]	auto[0]	212034	1			T1	1763		T3	14		T14	7708
all_values[2]	auto[0]	auto[1]	1676	1			T1	7		T3	5		T14	7
all_values[2]	auto[1]	auto[0]	98159991	1			T1	60172		T2	455819		T3	461381
all_values[2]	auto[1]	auto[1]	505620	1			T1	81		T2	3384		T3	3430