Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
313100 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
4530 |
auto[1] |
376986 |
1 |
|
|
T1 |
136 |
|
T2 |
4528 |
|
T13 |
378 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172904 |
1 |
|
|
T1 |
37 |
|
T2 |
1173 |
|
T3 |
1150 |
lower_val |
170412 |
1 |
|
|
T1 |
28 |
|
T2 |
1090 |
|
T3 |
1187 |
zero_val |
1748 |
1 |
|
|
T1 |
2 |
|
T2 |
7 |
|
T3 |
5 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
344590 |
1 |
|
|
T1 |
82 |
|
T2 |
2190 |
|
T3 |
2286 |
lower_val |
345476 |
1 |
|
|
T1 |
56 |
|
T2 |
2340 |
|
T3 |
2244 |
zero_val |
20 |
1 |
|
|
T175 |
2 |
|
T176 |
2 |
|
T177 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
1 |
17 |
94.44 |
1 |
Automatically Generated Cross Bins for entropy_timer_cross
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38949 |
1 |
|
|
T3 |
586 |
|
T13 |
1 |
|
T18 |
76 |
higher_val |
higher_val |
auto[1] |
47282 |
1 |
|
|
T1 |
20 |
|
T2 |
580 |
|
T13 |
54 |
higher_val |
lower_val |
auto[0] |
39347 |
1 |
|
|
T3 |
564 |
|
T14 |
1 |
|
T16 |
1 |
higher_val |
lower_val |
auto[1] |
47321 |
1 |
|
|
T1 |
17 |
|
T2 |
593 |
|
T13 |
41 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T176 |
1 |
|
T177 |
1 |
|
T178 |
1 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T179 |
1 |
|
T180 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
38508 |
1 |
|
|
T3 |
601 |
|
T18 |
75 |
|
T64 |
533 |
lower_val |
higher_val |
auto[1] |
46453 |
1 |
|
|
T1 |
19 |
|
T2 |
524 |
|
T13 |
44 |
lower_val |
lower_val |
auto[0] |
38803 |
1 |
|
|
T3 |
586 |
|
T18 |
81 |
|
T64 |
539 |
lower_val |
lower_val |
auto[1] |
46640 |
1 |
|
|
T1 |
9 |
|
T2 |
566 |
|
T13 |
36 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T175 |
1 |
|
T181 |
2 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
5 |
1 |
|
|
T179 |
1 |
|
T182 |
2 |
|
T183 |
1 |
zero_val |
higher_val |
auto[0] |
619 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
233 |
1 |
|
|
T2 |
1 |
|
T17 |
1 |
|
T22 |
2 |
zero_val |
lower_val |
auto[0] |
664 |
1 |
|
|
T3 |
5 |
|
T14 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
231 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T17 |
1 |
zero_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T175 |
1 |
|
- |
- |
|
- |
- |