Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98879321	1			T1	62023		T2	459203		T3	464830
all_pins[1]	98879321	1			T1	62023		T2	459203		T3	464830
all_pins[2]	98879321	1			T1	62023		T2	459203		T3	464830

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295913387	1			T1	183403		T2	137422		T3	139105
values[0x1]	724576	1			T1	2666		T2	3382		T3	3435
transitions[0x0=>0x1]	723241	1			T1	2648		T2	3382		T3	3435
transitions[0x1=>0x0]	723265	1			T1	2648		T2	3382		T3	3435

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98373869	1			T1	61943		T2	455821		T3	461395
all_pins[0]	values[0x1]	505452	1			T1	80		T2	3382		T3	3435
all_pins[0]	transitions[0x0=>0x1]	505442	1			T1	80		T2	3382		T3	3435
all_pins[0]	transitions[0x1=>0x0]	66	1			T40	3		T184	3		T185	3
all_pins[1]	values[0x0]	98879245	1			T1	62023		T2	459203		T3	464830
all_pins[1]	values[0x1]	76	1			T40	3		T184	3		T185	3
all_pins[1]	transitions[0x0=>0x1]	64	1			T40	3		T184	3		T185	3
all_pins[1]	transitions[0x1=>0x0]	219036	1			T1	2586		T23	12184		T24	5936
all_pins[2]	values[0x0]	98660273	1			T1	59437		T2	459203		T3	464830
all_pins[2]	values[0x1]	219048	1			T1	2586		T23	12184		T24	5936
all_pins[2]	transitions[0x0=>0x1]	217735	1			T1	2568		T23	12098		T24	5889
all_pins[2]	transitions[0x1=>0x0]	504163	1			T1	62		T2	3382		T3	3435