Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	587	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5254	1			T1	6		T14	24		T22	21
len_601_800	11967	1			T1	19		T14	59		T16	4
len_401_600	7879	1			T1	18		T14	34		T16	1
len_201_400	16218	1			T1	4		T2	251		T3	251
len_65_200	73565	1			T1	9		T2	680		T3	680
len_min_for_xof_require_squeeze	1010	1			T2	10		T3	10		T13	2
len_keccak_block_sizes[72]	748	1			T2	5		T3	5		T13	2
len_keccak_block_sizes[104]	758	1			T2	5		T3	5		T17	5
len_keccak_block_sizes[136]	746	1			T2	5		T3	5		T17	5
len_keccak_block_sizes[144]	289	1			T2	5		T3	5		T17	5
len_keccak_block_sizes[168]	280	1			T2	5		T3	5		T13	1
len_datapath_width	14028	1			T2	5		T3	5		T13	8
len_2_63	214422	1			T1	13		T2	1329		T3	1329
len_1	38	1			T13	1		T22	1		T139	1