Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10446300 |
1 |
|
|
T1 |
9163 |
|
T2 |
47900 |
|
T3 |
47900 |
auto[1] |
25303521 |
1 |
|
|
T1 |
13528 |
|
T2 |
141800 |
|
T3 |
141800 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35632124 |
1 |
|
|
T1 |
22643 |
|
T2 |
188764 |
|
T3 |
188764 |
triple_byte_access |
39180 |
1 |
|
|
T1 |
11 |
|
T2 |
310 |
|
T3 |
310 |
halfword_access |
39381 |
1 |
|
|
T1 |
14 |
|
T2 |
316 |
|
T3 |
316 |
byte_access |
39136 |
1 |
|
|
T1 |
23 |
|
T2 |
310 |
|
T3 |
310 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10328603 |
1 |
|
|
T1 |
9115 |
|
T2 |
46964 |
|
T3 |
46964 |
auto[0] |
triple_byte_access |
39180 |
1 |
|
|
T1 |
11 |
|
T2 |
310 |
|
T3 |
310 |
auto[0] |
halfword_access |
39381 |
1 |
|
|
T1 |
14 |
|
T2 |
316 |
|
T3 |
316 |
auto[0] |
byte_access |
39136 |
1 |
|
|
T1 |
23 |
|
T2 |
310 |
|
T3 |
310 |
auto[1] |
word_access |
25303521 |
1 |
|
|
T1 |
13528 |
|
T2 |
141800 |
|
T3 |
141800 |