Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
78.57 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 3 5 62.50


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 3 5 62.50 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10446300 1 T1 9163 T2 47900 T3 47900
auto[1] 25303521 1 T1 13528 T2 141800 T3 141800



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 35632124 1 T1 22643 T2 188764 T3 188764
triple_byte_access 39180 1 T1 11 T2 310 T3 310
halfword_access 39381 1 T1 14 T2 316 T3 316
byte_access 39136 1 T1 23 T2 310 T3 310



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 3 5 62.50 3


Automatically Generated Cross Bins for state_mask_share_cross

Uncovered bins
sharestate_read_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [triple_byte_access , halfword_access , byte_access] -- -- 3


Covered bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 10328603 1 T1 9115 T2 46964 T3 46964
auto[0] triple_byte_access 39180 1 T1 11 T2 310 T3 310
auto[0] halfword_access 39381 1 T1 14 T2 316 T3 316
auto[0] byte_access 39136 1 T1 23 T2 310 T3 310
auto[1] word_access 25303521 1 T1 13528 T2 141800 T3 141800

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%