Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99926081	1			T1	1748		T2	277		T3	113652
all_values[1]	99926081	1			T1	1748		T2	277		T3	113652
all_values[2]	99926081	1			T1	1748		T2	277		T3	113652

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

578776

1

T1

66

T13

7

T14

284

auto[1]

299199467

1

T1

5178

T2

831

T3

340956

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298252833

1

T1

4503

T2

798

T3

339840

auto[1]

1525410

1

T1

741

T2

33

T3

1116

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	190459	1			T1	47		T14	280		T15	1
all_values[0]	auto[0]	auto[1]	1928	1			T1	8		T14	4		T15	2
all_values[0]	auto[1]	auto[0]	99227152	1			T1	1454		T2	266		T3	113280
all_values[0]	auto[1]	auto[1]	506542	1			T1	239		T2	11		T3	372
all_values[1]	auto[0]	auto[0]	170583	1			T18	15		T29	108		T22	1088
all_values[1]	auto[0]	auto[1]	1516	1			T18	1		T29	1		T22	15
all_values[1]	auto[1]	auto[0]	99247028	1			T1	1501		T2	266		T3	113280
all_values[1]	auto[1]	auto[1]	506954	1			T1	247		T2	11		T3	372
all_values[2]	auto[0]	auto[0]	212687	1			T1	9		T13	4		T17	1
all_values[2]	auto[0]	auto[1]	1603	1			T1	2		T13	3		T17	2
all_values[2]	auto[1]	auto[0]	99204924	1			T1	1492		T2	266		T3	113280
all_values[2]	auto[1]	auto[1]	506867	1			T1	245		T2	11		T3	372