Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
339148 |
1 |
|
|
T1 |
334 |
|
T2 |
2 |
|
T3 |
492 |
auto[1] |
352966 |
1 |
|
|
T2 |
16 |
|
T12 |
182 |
|
T13 |
746 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173421 |
1 |
|
|
T1 |
88 |
|
T2 |
4 |
|
T3 |
138 |
lower_val |
171793 |
1 |
|
|
T1 |
74 |
|
T2 |
2 |
|
T3 |
106 |
zero_val |
1870 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346648 |
1 |
|
|
T1 |
178 |
|
T2 |
8 |
|
T3 |
254 |
lower_val |
345456 |
1 |
|
|
T1 |
156 |
|
T2 |
10 |
|
T3 |
238 |
zero_val |
10 |
1 |
|
|
T148 |
2 |
|
T149 |
2 |
|
T150 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val , zero_val] |
[zero_val] |
[auto[1]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42759 |
1 |
|
|
T1 |
51 |
|
T3 |
70 |
|
T14 |
43 |
higher_val |
higher_val |
auto[1] |
44283 |
1 |
|
|
T2 |
3 |
|
T12 |
26 |
|
T13 |
87 |
higher_val |
lower_val |
auto[0] |
42227 |
1 |
|
|
T1 |
37 |
|
T3 |
68 |
|
T14 |
41 |
higher_val |
lower_val |
auto[1] |
44148 |
1 |
|
|
T2 |
1 |
|
T12 |
23 |
|
T13 |
75 |
higher_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T149 |
1 |
|
T151 |
2 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42110 |
1 |
|
|
T1 |
37 |
|
T3 |
62 |
|
T14 |
63 |
lower_val |
higher_val |
auto[1] |
44046 |
1 |
|
|
T12 |
25 |
|
T13 |
81 |
|
T39 |
42 |
lower_val |
lower_val |
auto[0] |
41660 |
1 |
|
|
T1 |
37 |
|
T3 |
44 |
|
T14 |
56 |
lower_val |
lower_val |
auto[1] |
43975 |
1 |
|
|
T2 |
2 |
|
T12 |
25 |
|
T13 |
97 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T148 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
686 |
1 |
|
|
T1 |
2 |
|
T15 |
2 |
|
T39 |
1 |
zero_val |
higher_val |
auto[1] |
261 |
1 |
|
|
T13 |
2 |
|
T22 |
4 |
|
T62 |
3 |
zero_val |
lower_val |
auto[0] |
664 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
lower_val |
auto[1] |
258 |
1 |
|
|
T13 |
2 |
|
T22 |
5 |
|
T62 |
3 |
zero_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T152 |
1 |
|
- |
- |
|
- |
- |