Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99926081	1			T1	1748		T2	277		T3	113652
all_pins[1]	99926081	1			T1	1748		T2	277		T3	113652
all_pins[2]	99926081	1			T1	1748		T2	277		T3	113652

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298969264	1			T1	5005		T2	820		T3	340584
values[0x1]	808979	1			T1	239		T2	11		T3	372
transitions[0x0=>0x1]	807107	1			T1	239		T2	11		T3	372
transitions[0x1=>0x0]	807131	1			T1	239		T2	11		T3	372

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99419539	1			T1	1509		T2	266		T3	113280
all_pins[0]	values[0x1]	506542	1			T1	239		T2	11		T3	372
all_pins[0]	transitions[0x0=>0x1]	506531	1			T1	239		T2	11		T3	372
all_pins[0]	transitions[0x1=>0x0]	61	1			T75	2		T158	4		T159	6
all_pins[1]	values[0x0]	99926009	1			T1	1748		T2	277		T3	113652
all_pins[1]	values[0x1]	72	1			T75	2		T158	4		T159	6
all_pins[1]	transitions[0x0=>0x1]	64	1			T75	2		T158	4		T159	6
all_pins[1]	transitions[0x1=>0x0]	302357	1			T14	1033		T22	1407		T24	4734
all_pins[2]	values[0x0]	99623716	1			T1	1748		T2	277		T3	113652
all_pins[2]	values[0x1]	302365	1			T14	1033		T22	1407		T24	4734
all_pins[2]	transitions[0x0=>0x1]	300512	1			T14	1033		T22	1399		T24	4707
all_pins[2]	transitions[0x1=>0x0]	504713	1			T1	239		T2	11		T3	372