Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	651	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5327	1			T12	20		T14	21		T18	3
len_601_800	12146	1			T12	36		T14	63		T18	5
len_401_600	7812	1			T12	12		T14	33		T18	1
len_201_400	16380	1			T12	8		T14	18		T29	2
len_65_200	73879	1			T1	80		T12	11		T14	8
len_min_for_xof_require_squeeze	1012	1			T39	1		T62	9		T84	9
len_keccak_block_sizes[72]	755	1			T1	1		T39	1		T62	9
len_keccak_block_sizes[104]	745	1			T1	2		T39	2		T62	9
len_keccak_block_sizes[136]	759	1			T39	1		T22	2		T62	9
len_keccak_block_sizes[144]	288	1			T75	1		T173	5		T25	1
len_keccak_block_sizes[168]	278	1			T173	5		T128	1		T122	1
len_datapath_width	14059	1			T1	5		T2	3		T3	246
len_2_63	214778	1			T1	82		T2	6		T12	3
len_1	70	1			T12	1		T39	1		T61	1