Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100439290	1			T1	292717		T2	222807		T3	9169
all_values[1]	100439290	1			T1	292717		T2	222807		T3	9169
all_values[2]	100439290	1			T1	292717		T2	222807		T3	9169

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

479445

1

T1

1574

T2

15

T3

36

auto[1]

300838425

1

T1

876577

T2

668406

T3

27471

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299801850

1

T1

877284

T2

666633

T3

26853

auto[1]

1516020

1

T1

867

T2

1788

T3

654

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	160972	1			T1	785		T15	62		T18	238
all_values[0]	auto[0]	auto[1]	2011	1			T1	2		T15	6		T18	2
all_values[0]	auto[1]	auto[0]	99772978	1			T1	291643		T2	222211		T3	8951
all_values[0]	auto[1]	auto[1]	503329	1			T1	287		T2	596		T3	218
all_values[1]	auto[0]	auto[0]	144451	1			T2	10		T3	13		T13	2
all_values[1]	auto[0]	auto[1]	1475	1			T2	5		T3	2		T13	1
all_values[1]	auto[1]	auto[0]	99789499	1			T1	292428		T2	222201		T3	8938
all_values[1]	auto[1]	auto[1]	503865	1			T1	289		T2	591		T3	216
all_values[2]	auto[0]	auto[0]	168927	1			T1	785		T3	20		T13	2
all_values[2]	auto[0]	auto[1]	1609	1			T1	2		T3	1		T13	1
all_values[2]	auto[1]	auto[0]	99765023	1			T1	291643		T2	222211		T3	8931
all_values[2]	auto[1]	auto[1]	503731	1			T1	287		T2	596		T3	217