Summary for Variable key_len
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for key_len
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Key128] |
65795 |
1 |
|
|
T1 |
30 |
|
T2 |
73 |
|
T3 |
19 |
auto[Key192] |
65776 |
1 |
|
|
T1 |
34 |
|
T2 |
80 |
|
T3 |
9 |
auto[Key256] |
80269 |
1 |
|
|
T1 |
39 |
|
T2 |
72 |
|
T3 |
90 |
auto[Key384] |
65885 |
1 |
|
|
T1 |
41 |
|
T2 |
74 |
|
T3 |
10 |
auto[Key512] |
65324 |
1 |
|
|
T1 |
45 |
|
T2 |
91 |
|
T3 |
11 |
Summary for Variable kmac_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
310088 |
1 |
|
|
T1 |
58 |
|
T2 |
390 |
|
T3 |
32 |
auto[1] |
32961 |
1 |
|
|
T1 |
131 |
|
T3 |
107 |
|
T15 |
9 |
Summary for Variable mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
3 |
0 |
3 |
100.00 |
Automatically Generated Bins for mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[Sha3] |
67346 |
1 |
|
|
T1 |
4 |
|
T2 |
390 |
|
T3 |
3 |
auto[Shake] |
239394 |
1 |
|
|
T1 |
54 |
|
T3 |
29 |
|
T17 |
38 |
auto[CShake] |
36309 |
1 |
|
|
T1 |
131 |
|
T3 |
107 |
|
T15 |
9 |
Summary for Variable msg_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for msg_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171568 |
1 |
|
|
T1 |
92 |
|
T2 |
195 |
|
T3 |
68 |
auto[1] |
171481 |
1 |
|
|
T1 |
97 |
|
T2 |
195 |
|
T3 |
71 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
333387 |
1 |
|
|
T1 |
189 |
|
T2 |
390 |
|
T3 |
96 |
auto[1] |
9662 |
1 |
|
|
T3 |
43 |
|
T17 |
12 |
|
T18 |
2 |
Summary for Variable state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_endian
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
171537 |
1 |
|
|
T1 |
90 |
|
T2 |
189 |
|
T3 |
72 |
auto[1] |
171512 |
1 |
|
|
T1 |
99 |
|
T2 |
201 |
|
T3 |
67 |
Summary for Variable strength
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
5 |
0 |
5 |
100.00 |
Automatically Generated Bins for strength
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[L128] |
136708 |
1 |
|
|
T1 |
86 |
|
T3 |
74 |
|
T15 |
6 |
auto[L224] |
19869 |
1 |
|
|
T1 |
2 |
|
T2 |
390 |
|
T3 |
2 |
auto[L256] |
158006 |
1 |
|
|
T1 |
101 |
|
T3 |
62 |
|
T15 |
3 |
auto[L384] |
15834 |
1 |
|
|
T3 |
1 |
|
T13 |
310 |
|
T36 |
310 |
auto[L512] |
12632 |
1 |
|
|
T16 |
246 |
|
T87 |
5 |
|
T143 |
1 |
Summary for Variable xof_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for xof_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
324727 |
1 |
|
|
T1 |
98 |
|
T2 |
390 |
|
T3 |
59 |
auto[1] |
18322 |
1 |
|
|
T1 |
91 |
|
T3 |
80 |
|
T15 |
9 |
Summary for Cross kmac_cross
Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for kmac_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
32961 |
1 |
|
|
T1 |
131 |
|
T3 |
107 |
|
T15 |
9 |
Summary for Cross cshake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for cshake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
36309 |
1 |
|
|
T1 |
131 |
|
T3 |
107 |
|
T15 |
9 |
Summary for Cross shake_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for shake_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
239394 |
1 |
|
|
T1 |
54 |
|
T3 |
29 |
|
T17 |
38 |
Summary for Cross sha3_cross
Samples crossed: mode strength msg_endian state_endian
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
1 |
0 |
1 |
100.00 |
|
User Defined Cross Bins for sha3_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
invalid_mode |
0 |
Excluded |
invalid_strength |
0 |
Excluded |
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
valid |
67346 |
1 |
|
|
T1 |
4 |
|
T2 |
390 |
|
T3 |
3 |