Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100439290	1			T1	292717		T2	222807		T3	9169
all_pins[1]	100439290	1			T1	292717		T2	222807		T3	9169
all_pins[2]	100439290	1			T1	292717		T2	222807		T3	9169

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300526146	1			T1	877864		T2	667825		T3	27289
values[0x1]	791724	1			T1	287		T2	596		T3	218
transitions[0x0=>0x1]	789968	1			T1	287		T2	596		T3	218
transitions[0x1=>0x0]	789992	1			T1	287		T2	596		T3	218

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99935961	1			T1	292430		T2	222211		T3	8951
all_pins[0]	values[0x1]	503329	1			T1	287		T2	596		T3	218
all_pins[0]	transitions[0x0=>0x1]	503316	1			T1	287		T2	596		T3	218
all_pins[0]	transitions[0x1=>0x0]	55	1			T41	3		T180	3		T181	3
all_pins[1]	values[0x0]	100439222	1			T1	292717		T2	222807		T3	9169
all_pins[1]	values[0x1]	68	1			T41	3		T180	3		T181	3
all_pins[1]	transitions[0x0=>0x1]	51	1			T41	3		T180	3		T181	3
all_pins[1]	transitions[0x1=>0x0]	288310	1			T27	582		T22	6182		T50	1
all_pins[2]	values[0x0]	100150963	1			T1	292717		T2	222807		T3	9169
all_pins[2]	values[0x1]	288327	1			T27	582		T22	6182		T50	1
all_pins[2]	transitions[0x0=>0x1]	286601	1			T27	582		T22	6143		T50	1
all_pins[2]	transitions[0x1=>0x0]	501627	1			T1	287		T2	596		T3	218