Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337898 |
1 |
|
|
T1 |
188 |
|
T2 |
375 |
|
T3 |
138 |
auto[1] |
3483 |
1 |
|
|
T14 |
1 |
|
T17 |
15 |
|
T18 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
304551 |
1 |
|
|
T1 |
58 |
|
T2 |
375 |
|
T3 |
32 |
auto[1] |
36830 |
1 |
|
|
T1 |
130 |
|
T3 |
106 |
|
T14 |
1 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
328130 |
1 |
|
|
T1 |
188 |
|
T2 |
375 |
|
T3 |
95 |
auto[1] |
13251 |
1 |
|
|
T3 |
43 |
|
T14 |
1 |
|
T17 |
27 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13251 |
1 |
|
|
T3 |
43 |
|
T14 |
1 |
|
T17 |
27 |
sw_kmac_invalid_sideload |
328130 |
1 |
|
|
T1 |
188 |
|
T2 |
375 |
|
T3 |
95 |
app_valid_sideload |
13251 |
1 |
|
|
T3 |
43 |
|
T14 |
1 |
|
T17 |
27 |
app_invalid_sideload |
328130 |
1 |
|
|
T1 |
188 |
|
T2 |
375 |
|
T3 |
95 |