Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99778767	1			T2	1383		T3	162058		T11	158001
all_values[1]	99778767	1			T2	1383		T3	162058		T11	158001
all_values[2]	99778767	1			T2	1383		T3	162058		T11	158001

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

631075

1

T2

86

T3

3

T11

7

auto[1]

298705226

1

T2

4063

T3

486171

T11

473996

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297814413

1

T2

3804

T3

484797

T11

472611

auto[1]

1521888

1

T2

345

T3

1377

T11

1392

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192101	1			T2	32		T11	3		T12	187
all_values[0]	auto[0]	auto[1]	2031	1			T2	2		T11	4		T12	4
all_values[0]	auto[1]	auto[0]	99079370	1			T2	1236		T3	161599		T11	157534
all_values[0]	auto[1]	auto[1]	505265	1			T2	113		T3	459		T11	460
all_values[1]	auto[0]	auto[0]	214714	1			T12	1		T25	1		T73	7
all_values[1]	auto[0]	auto[1]	1523	1			T73	4		T74	2		T64	1
all_values[1]	auto[1]	auto[0]	99056757	1			T2	1268		T3	161599		T11	157537
all_values[1]	auto[1]	auto[1]	505773	1			T2	115		T3	459		T11	464
all_values[2]	auto[0]	auto[0]	219129	1			T2	49		T3	2		T14	8
all_values[2]	auto[0]	auto[1]	1577	1			T2	3		T3	1		T14	2
all_values[2]	auto[1]	auto[0]	99052342	1			T2	1219		T3	161597		T11	157537
all_values[2]	auto[1]	auto[1]	505719	1			T2	112		T3	458		T11	464