Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
331642 |
1 |
|
|
T2 |
154 |
|
T3 |
620 |
|
T11 |
2 |
auto[1] |
358240 |
1 |
|
|
T11 |
618 |
|
T15 |
16 |
|
T17 |
4672 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173419 |
1 |
|
|
T2 |
26 |
|
T3 |
166 |
|
T11 |
160 |
lower_val |
170996 |
1 |
|
|
T2 |
37 |
|
T3 |
137 |
|
T11 |
168 |
zero_val |
1770 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T11 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345082 |
1 |
|
|
T2 |
90 |
|
T3 |
306 |
|
T11 |
296 |
lower_val |
344790 |
1 |
|
|
T2 |
64 |
|
T3 |
314 |
|
T11 |
324 |
zero_val |
10 |
1 |
|
|
T64 |
2 |
|
T139 |
2 |
|
T140 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
41815 |
1 |
|
|
T2 |
17 |
|
T3 |
78 |
|
T12 |
29 |
higher_val |
higher_val |
auto[1] |
45002 |
1 |
|
|
T11 |
82 |
|
T15 |
3 |
|
T17 |
620 |
higher_val |
lower_val |
auto[0] |
41756 |
1 |
|
|
T2 |
9 |
|
T3 |
88 |
|
T12 |
23 |
higher_val |
lower_val |
auto[1] |
44844 |
1 |
|
|
T11 |
78 |
|
T15 |
2 |
|
T17 |
639 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T141 |
1 |
|
T142 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
40780 |
1 |
|
|
T2 |
22 |
|
T3 |
75 |
|
T12 |
15 |
lower_val |
higher_val |
auto[1] |
44679 |
1 |
|
|
T11 |
85 |
|
T15 |
1 |
|
T17 |
562 |
lower_val |
lower_val |
auto[0] |
41421 |
1 |
|
|
T2 |
15 |
|
T3 |
62 |
|
T11 |
1 |
lower_val |
lower_val |
auto[1] |
44111 |
1 |
|
|
T11 |
82 |
|
T15 |
1 |
|
T17 |
568 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T64 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
4 |
1 |
|
|
T139 |
1 |
|
T140 |
2 |
|
T142 |
1 |
zero_val |
higher_val |
auto[0] |
658 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
243 |
1 |
|
|
T17 |
6 |
|
T22 |
4 |
|
T26 |
1 |
zero_val |
lower_val |
auto[0] |
622 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
247 |
1 |
|
|
T17 |
4 |
|
T22 |
2 |
|
T26 |
1 |