Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99778767	1			T2	1383		T3	162058		T11	158001
all_pins[1]	99778767	1			T2	1383		T3	162058		T11	158001
all_pins[2]	99778767	1			T2	1383		T3	162058		T11	158001

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298578825	1			T2	4036		T3	485715		T11	473543
values[0x1]	757476	1			T2	113		T3	459		T11	460
transitions[0x0=>0x1]	755971	1			T2	113		T3	459		T11	460
transitions[0x1=>0x0]	755994	1			T2	113		T3	459		T11	460

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99273502	1			T2	1270		T3	161599		T11	157541
all_pins[0]	values[0x1]	505265	1			T2	113		T3	459		T11	460
all_pins[0]	transitions[0x0=>0x1]	505254	1			T2	113		T3	459		T11	460
all_pins[0]	transitions[0x1=>0x0]	63	1			T152	4		T153	5		T154	5
all_pins[1]	values[0x0]	99778693	1			T2	1383		T3	162058		T11	158001
all_pins[1]	values[0x1]	74	1			T152	4		T153	5		T154	5
all_pins[1]	transitions[0x0=>0x1]	65	1			T152	4		T153	5		T154	5
all_pins[1]	transitions[0x1=>0x0]	252128	1			T12	7875		T28	767		T29	374
all_pins[2]	values[0x0]	99526630	1			T2	1383		T3	162058		T11	158001
all_pins[2]	values[0x1]	252137	1			T12	7875		T28	767		T29	374
all_pins[2]	transitions[0x0=>0x1]	250652	1			T12	7826		T28	767		T29	374
all_pins[2]	transitions[0x1=>0x0]	503803	1			T2	113		T3	459		T11	460