Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10455340 |
1 |
|
|
T2 |
12263 |
|
T3 |
3720 |
|
T11 |
3720 |
auto[1] |
25316994 |
1 |
|
|
T2 |
17640 |
|
T3 |
15500 |
|
T11 |
15500 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
35654731 |
1 |
|
|
T2 |
29847 |
|
T3 |
19220 |
|
T11 |
19220 |
triple_byte_access |
39174 |
1 |
|
|
T2 |
20 |
|
T12 |
15 |
|
T14 |
32 |
halfword_access |
39399 |
1 |
|
|
T2 |
19 |
|
T12 |
16 |
|
T14 |
27 |
byte_access |
39030 |
1 |
|
|
T2 |
17 |
|
T12 |
11 |
|
T14 |
31 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10337737 |
1 |
|
|
T2 |
12207 |
|
T3 |
3720 |
|
T11 |
3720 |
auto[0] |
triple_byte_access |
39174 |
1 |
|
|
T2 |
20 |
|
T12 |
15 |
|
T14 |
32 |
auto[0] |
halfword_access |
39399 |
1 |
|
|
T2 |
19 |
|
T12 |
16 |
|
T14 |
27 |
auto[0] |
byte_access |
39030 |
1 |
|
|
T2 |
17 |
|
T12 |
11 |
|
T14 |
31 |
auto[1] |
word_access |
25316994 |
1 |
|
|
T2 |
17640 |
|
T3 |
15500 |
|
T11 |
15500 |