Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99821902	1			T2	1637		T3	60766		T13	16066
all_values[1]	99821902	1			T2	1637		T3	60766		T13	16066
all_values[2]	99821902	1			T2	1637		T3	60766		T13	16066

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575354

1

T2

8

T3

2275

T13

1994

auto[1]

298890352

1

T2

4903

T3

180023

T13

46204

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297945891

1

T2

4170

T3

181443

T13

47715

auto[1]

1519815

1

T2

741

T3

855

T13

483

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	207601	1			T2	2		T3	563		T14	4
all_values[0]	auto[0]	auto[1]	1961	1			T2	2		T3	8		T14	2
all_values[0]	auto[1]	auto[0]	99107696	1			T2	1388		T3	59918		T13	15905
all_values[0]	auto[1]	auto[1]	504644	1			T2	245		T3	277		T13	161
all_values[1]	auto[0]	auto[0]	201657	1			T2	2		T3	688		T13	640
all_values[1]	auto[0]	auto[1]	1567	1			T2	2		T3	17		T13	6
all_values[1]	auto[1]	auto[0]	99113640	1			T2	1388		T3	59793		T13	15265
all_values[1]	auto[1]	auto[1]	505038	1			T2	245		T3	268		T13	155
all_values[2]	auto[0]	auto[0]	161179	1			T3	988		T13	1335		T15	23
all_values[2]	auto[0]	auto[1]	1389	1			T3	11		T13	13		T15	13
all_values[2]	auto[1]	auto[0]	99154118	1			T2	1390		T3	59493		T13	14570
all_values[2]	auto[1]	auto[1]	505216	1			T2	247		T3	274		T13	148