Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
335958 |
1 |
|
|
T2 |
324 |
|
T3 |
138 |
|
T13 |
2 |
auto[1] |
352788 |
1 |
|
|
T3 |
322 |
|
T13 |
206 |
|
T15 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172690 |
1 |
|
|
T2 |
100 |
|
T3 |
107 |
|
T13 |
51 |
lower_val |
170556 |
1 |
|
|
T2 |
85 |
|
T3 |
109 |
|
T13 |
46 |
zero_val |
1800 |
1 |
|
|
T2 |
1 |
|
T3 |
8 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
345194 |
1 |
|
|
T2 |
162 |
|
T3 |
224 |
|
T13 |
112 |
lower_val |
343540 |
1 |
|
|
T2 |
162 |
|
T3 |
236 |
|
T13 |
96 |
zero_val |
12 |
1 |
|
|
T65 |
2 |
|
T155 |
2 |
|
T156 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42182 |
1 |
|
|
T2 |
48 |
|
T3 |
9 |
|
T14 |
1 |
higher_val |
higher_val |
auto[1] |
44409 |
1 |
|
|
T3 |
37 |
|
T13 |
33 |
|
T15 |
59 |
higher_val |
lower_val |
auto[0] |
41803 |
1 |
|
|
T2 |
52 |
|
T3 |
15 |
|
T14 |
1 |
higher_val |
lower_val |
auto[1] |
44295 |
1 |
|
|
T3 |
46 |
|
T13 |
18 |
|
T15 |
63 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
41791 |
1 |
|
|
T2 |
45 |
|
T3 |
14 |
|
T14 |
2 |
lower_val |
higher_val |
auto[1] |
43770 |
1 |
|
|
T3 |
38 |
|
T13 |
23 |
|
T15 |
62 |
lower_val |
lower_val |
auto[0] |
41518 |
1 |
|
|
T2 |
40 |
|
T3 |
15 |
|
T14 |
2 |
lower_val |
lower_val |
auto[1] |
43471 |
1 |
|
|
T3 |
42 |
|
T13 |
23 |
|
T15 |
68 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T155 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
5 |
1 |
|
|
T65 |
1 |
|
T156 |
1 |
|
T158 |
2 |
zero_val |
higher_val |
auto[0] |
672 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
zero_val |
higher_val |
auto[1] |
218 |
1 |
|
|
T3 |
2 |
|
T159 |
2 |
|
T160 |
1 |
zero_val |
lower_val |
auto[0] |
691 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
219 |
1 |
|
|
T3 |
2 |
|
T15 |
6 |
|
T159 |
2 |