Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8863	1			T3	4		T17	24		T18	24
len_5001_7500	13894	1			T3	18		T15	33		T17	24
len_2501_5000	9143	1			T3	1		T15	34		T17	24
len_1025_2500	5324	1			T15	20		T17	14		T18	14
len_769_1024	5820	1			T3	21		T13	18		T15	4
len_513_768	6199	1			T3	26		T13	39		T15	3
len_257_512	20521	1			T3	28		T13	30		T15	4
len_0_256	257400	1			T2	162		T3	90		T13	17
len_keccak_block_sizes[72]	724	1			T15	2		T17	2		T18	2
len_keccak_block_sizes[104]	618	1			T17	2		T18	2		T140	2
len_keccak_block_sizes[136]	515	1			T140	2		T141	2		T185	3
len_keccak_block_sizes[144]	417	1			T185	3		T186	3		T159	2
len_keccak_block_sizes[168]	318	1			T185	3		T186	3		T160	3
len_1	759	1			T2	3		T3	1		T15	2
len_0	1232	1			T2	5		T3	3		T15	2